• Title/Summary/Keyword: Parasitic characteristics

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Decrease of Parasitic Capacitance for Improvement of RF Performance of Multi-finger MOSFETs in 90-nm CMOS Technology

  • Jang, Seong-Yong;Kwon, Sung-Kyu;Shin, Jong-Kwan;Yu, Jae-Nam;Oh, Sun-Ho;Jeong, Jin-Woong;Song, Hyeong-Sub;Kim, Choul-Young;Lee, Ga-Won;Lee, Hi-Deok
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.15 no.2
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    • pp.312-317
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    • 2015
  • In this paper, the RF characteristics of multi-finger MOSFETs were improved by decreasing the parasitic capacitance in spite of increased gate resistance in a 90-nm CMOS technology. Two types of device structures were designed to compare the parasitic capacitance in the gate-to-source ($C_{gs}$) and gate-to-drain ($C_{gd}$) configurations. The radio frequency (RF) performance of multi-finger MOSFETs, such as cut-off frequency ($f_T$) and maximum-oscillation frequency ($f_{max}$) improved by approximately 10% by reducing the parasitic capacitance about 8.2% while maintaining the DC performance.

Passive parasitic UWB antenna capable of switched beam-forming in the WLAN frequency band using an optimal reactance load algorithm

  • Lee, Jung-Nam;Lee, Yong-Ho;Lee, Kwang-Chun;Kim, Tae Joong
    • ETRI Journal
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    • v.41 no.6
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    • pp.715-730
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    • 2019
  • We propose a switched beam-forming antenna that satisfies not only ultra-wideband characteristics but also beam-forming in the WLAN frequency band using an ultra-wideband antenna and passive parasitic elements applying a broadband optimal reactance load algorithm. We design a power and phase estimation function and an error correction function by re-analyzing and normalizing all the components of the parasitic array using control system engineering. The proposed antenna is compared with an antenna with a pin diode and reactance load value, respectively. The pin diode is located between the passive parasitic elements and ground plane. An antenna beam can be formed in eight directions according to the pin diode ON (reflector)/OFF (director) state. The antenna with a reactance load value achieves a better VSWR and gain than the antenna with a pin diode. We confirm that a beam is formed in eight directions owing to the RF switch operation, and the measured peak gain is 7 dBi at 2.45 GHz and 10 dBi at 5.8 GHz.

A Study on the Characteristics Analysis of Hybrid Choke Coil with Reduced Parasitic Capacitance suitable for LED-TV SMPS (LED-TV용(用) 전원장치에 적합한 기생 커패시턴스 저감형 Hybrid 초크 코일의 특성 해석에 관한 연구)

  • Lee, Jong-Hyeon;Kim, Gu-Yong;Kim, Jong-Hae
    • Journal of IKEEE
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    • v.22 no.1
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    • pp.185-188
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    • 2018
  • This paper describes the parasitic capacitance modeling according to the coil structure, section bobbin and winding method for hybrid choke coil with reduced parasitic capacitance capable of the EMI attenuation of broad bands from lower frequency to higher frequency applied in the EMI attenuation filter of LED-TV SMPS. Especially, the hybrid choke coil with reduced parasitic capacitance($C_p$) proposed in this paper can reduces the parasitic capacitance($C_p$) by adopting the winding methods of rectangular copper wire, compared to the conventional common mode choke coil with the winding method of automatic type. The first resonant frequency of the proposed hybrid choke coil has a tendency to increase as the parasitic capacitance is smaller and its impedance characteristics, especially in the high frequency bands, improves as the first resonant frequency increases. In the future, the proposed hybrid choke coil with reduced parasitic capacitance shows it can be actually utilized in not only LED-TV SMPS but also various applications such as LED Lighting, Note-PC Adapter, and so forth.

Characteristics of Lateral Structure Transistor (횡방향 구조 트랜지스터의 특성)

  • 이정환;서희돈
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.13 no.12
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    • pp.977-982
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    • 2000
  • Conventional transistors which have vertical structure show increased parasitic capacitance characteristics in accordance with the increase of non-active base area and collector area. These consequently have disadvantage for high speed switching performance. In this paper, a lateral structure transistor which has minimized parasitic capacitance by using SDB(Silicon Direct Bonding) wafer and oxide sidewall isolation utilizing silicon trench technology is presented. Its structural characteristics are designed by ATHENA(SUPREM4), the process simulator from SILVACO International, and its performance is proven by ATLAS, the device simulator from SILVACO International. The performance of the proposed lateral structure transistor is certified through the V$\_$CE/-I$\_$C/ characteristics curve, h$\_$FE/-I$\_$C/ characteristics, and GP-plot. Cutoff Frequency is 13.7㎓.

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Design and Implementation of UWB Antenna with Dual Band Rejection Characteristics (이중 대역저지 특성을 가지는 UWB 안테나 설계 및 구현)

  • Yang, Woon Geun;Nam, Tae Hyeon
    • Journal of IKEEE
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    • v.22 no.2
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    • pp.413-419
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    • 2018
  • An UWB(Ultra Wide Band) antenna with band rejection characteristics is designed and implemented. A planar radiation patch with slot, parasitic elements on both sides of strip and ground plane on back side consist the proposed antenna. The slot in the radiation patch and parasitic elements contribute corresponding bands rejection characteristics. The slot contributes for WiMAX(World interoperability for Microwave Access, 3.30~3.70 GHz) band rejection and parasitic elements contribute for X-Band(7.25~8.395 GHz) rejection. Ansoft's HFSS(High Frequency Structure Simulator) was used to design the proposed antenna and performance simulations. Simulation result showed VSWR(Voltage Standing Wave Ratio) less than 2.0 for UWB band except for dual rejection bands of 3.30~3.86 GHz and 7.21~8.39 GHz. And VSWR measurement result for the implemented antenna shows less than 2.0 for 3.10~10.60 GHz band except dual rejection bands of 3.25~3.71 GHz and 7.25~8.46 GHz.

The Forward Characteristics of A New Lateral Thyristor with Current Saturation (전류포화특성을 갖는 새로운 이중게이트 수평형 사이리스터의 순방향 특성)

  • Lee, Yu-Sang;Choe, Yeon-Ik;Han, Min-Gu
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.48 no.12
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    • pp.773-776
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    • 1999
  • A newly proposed lateral dual-gate thyristor was fabricated and measured, which has excellent current saturation characteristics of $1200A/cm^2$ even at an anode-gate voltage of 29V, through the elimination of the structurally existing parasitic thyristor. And through the comparison with the LIGBT, the excellent current saturation characteristics of a newly proposed device was verified.

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Lateral Structure Transistor by Silicon Direct Bonding Technology (실리콘 직접접합 기술을 이용한 횡방향 구조 트랜지스터)

  • 이정환;서희돈
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2000.07a
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    • pp.759-762
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    • 2000
  • Present transistors which have vertical structure show increased parasitic capacitance characteristics in accordance with the increase of non-active base area and collector area, consequently have disadvantage for high speed switching performance. In this paper, a horizontal structure transistor which has minimized parasitic capacitance in virtue of SDB(Silicon Direct Bonding) wafer and oxide sidewall isolation utilizing silicon trench technology is presented. Its structural characteristics were designed by ATHENA(SUPREM4), the process simulator from SILVACO International, and its performance was proven by ATLAS, the device simulator from SILVACO International. The performance of the proposed horizontal structure transistor was certified through the VCE-lC characteristics curve, $h_{FE}$ -IC characteristics, and GP-plot.

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Influence of Parasitic Resistances and Transistor Asymmetries on Read Operation of High-Resistor SRAM Cells (기생저항 및 트랜지스터 비대칭이 고저항 SRAM 셀의 읽기동작에 미치는 영향)

  • Choi, Jin-Young;Choi, Won-Sang
    • Journal of IKEEE
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    • v.1 no.1 s.1
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    • pp.11-18
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    • 1997
  • By utilizing the technique to monitor the DC cell node voltages through circuit simulation, degradation of the static read operating margin In high load-resistor SRAM cell was examined, which is caused by parasitic resistances and transistor asymmetries in this cell structure. By selectively adding the parasitic resistances to an ideal cell, the influence of each parasitic resistance on the operating margin was examined, and then the cases with parasitic resistances in pairs were also examined. By selectively changing the channel width of cell transistors to generate cell asymmetry, the influence of cell asymmetry on the operating margin was also examined. Analyses on the operating margins were performed by comparing the supply voltage values at which two cell node voltages merge to a single value and the differences of cell node voltages at VDD=5V in the simulated node voltage characteristics. By determining the parasitic resistances and the transistor asymmetries which give the most serious effect on the static read-operation of SRAM cell from this analysis based on circuit simulated, a criteria was provided, which can be referred in the design of new SRAM cell structures.

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Design of Multiband Repeater Antenna with Fire-Fighting Band for In-Building Mobile Communication (소방무선대역을 포함하는 인빌딩용 다중대역 중계기 안테나 설계)

  • Kim, Sung-Min;Min, Kyeong-Sik
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.27 no.6
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    • pp.495-503
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    • 2016
  • This paper proposes the design of multiband repeater antenna with fire-fighting band for in-building mobile communication. The proposed antenna is composed of a center monopole and 4 parasitic elements on a circular plate. In order to realize good reflection coefficients at the multiband, mutual coupling between 4 parasitic elements and center monopole antenna is considered. The important parameters such as distance between parasitic element and a center monopole, and each height of a center monopole and 4 parasitic elements are simulated to obtain good antenna characteristics at the multiband. The diameter of 4 parasitic elements and a center monopole was fixed to 10 mm for easy design and manufacturing. The measurement results of reflection coefficients, 2-D patterns and gain agreed well with their simulation ones.

Difference of Gall Formation Rates and Parasitic Rates of Thecodiplosis japonensis (Diptera: Ceidomyiidae) Larvae in Pine Forests around Urban and Mountain Villages

  • Kim, Jongkyung;Ha, Manleung;Lee, Sanggon;Kim, Hyun;Lee, Chongkyu
    • Journal of Forest and Environmental Science
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    • v.36 no.4
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    • pp.290-297
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    • 2020
  • This study analyzed and compared the damage rate, natural parasitic rate, and the morphological characteristics of Thecodiplosis japonensis larvae, which inhabit forest areas as control areas to large urban areas in 2018 and 2019. This research was conducted to provide basic data for the management of Thecodiplosis japonensis, which harm pine needles, and the results were as follows. First, the gall formation rate of Thecodiplosis japonensis collected from urban areas was upper-crown 35.59% and 34.25%, mid-crown 25.57% and 27.95%, and lower-crown 25.34% and 26.61%; the gall formation rate of Thecodiplosis japonensis was in the order of upper-crown>mid-crown>lower-crown in 2018 and 2019, respectively. In the control areas, the gall formation rates of Thecodiplosis japonensis in mountain villages in 2018 and 2019 were upper-crown 17.72% and 21.78%, mid-crown 13.85% and 16.97%, and lower-crown 15.12% and 15.79%; thus, in the order of upper-crown>lower-crown>mid-crown. The number of larvae in the galls of needles damaged by Thecodiplosis japonensis was as follows: the average number of larvae in the pine trees of urban areas was 9 and 8 in the upper-crown, 7 and 8 in the mid-crown, and 6 and 7 in the lower-crown respectively. This shows that the number of larvae was fewer in the lower-crown than the upper-crown, and that the number of larvae was higher in 2018 than in 2019. For natural parasitic rate of Thecodiplosis japonensis, the gall formation rate and natural parasitic rate of Thecodiplosis japonensis were surveyed; the natural parasitic rate was 12.5% and 11.8% in urban areas while the rate was 21.7% and 20.9% in mountain villages in respectively in 2018 and 2019.