• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.393-394
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• 2008

This paper presents a new method to extract the substrate resistance by fitting current-dependent base resistance of parasitic BJT without a complex RF extraction method. The extracted substrate resistance values using the new method match well with those using the RF one, verifying the accuracy of the proposed DC technique.

• The Transactions of the Korean Institute of Power Electronics
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• v.16 no.5
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• pp.511-520
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• 2011

Nowadays, industry of smart grid is important for practical use of the renewable energy. In this situation, it is important to use the energy storage to make more stable and efficient renewable energy sources. The power conditioning systems consist in a boost converter which makes renewable energy source connected with the grid-connected inverter and the charger/discharger which takes the energy transfer between the boost converter and an energy storage. The effects on the controller design of each converter must be investigated to avoid the instability of the entire system. small-signal modelling of the boost converter and charger/discharger have been done and a controller design example is also presented. In this paper, effects on the controller design of the boost converter and the charger/discharger are investigated according to the existence of the parasitic resistance of the boost converter. In conclusion, the parasitic resistance of the inductor should be considered from the aspect of both the frequency domain analysis and time domain simulation using both MATLAB and PSIM.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.5
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• pp.785-793
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• 2016

This paper analyzes an LCL-type isolated dc-dc converter operating for constant output voltage in the continuous conduction mode(CCM) with resistances of parasitic losses-static drain-source on resistance of power switch, ESR of resonant network(L-C-L)-using a high loaded quality factor Q assumptions and fourier series techniques. Simple analytical expressions for performance characteristics are derived under steady-state conditions for designing and understanding the behavior of the proposed converter. The voltage-driven rectifier is analyzed, taking into account the diode threshold voltage and the diode forward resistance. Experimental results measured for a proposed converter at low input voltage and various load resistances show agreement to the theoretical performance predicted by the analysis within maximum 4% error. Especially in the case of low output voltages and large loads, It is been observed that introduction of both rectifier and the parasitic components of converter had considerable effect on the performance.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.6
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• pp.876-885
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• 2000

A new and simple method is presented for determining the parasitic resistances of MESFET and HEMT from the measured S-parameters under normal active bias without depending on additional DC measurements or iteration or optimization process. The presented method is based on the fact that the difference between source resistance(Rs) and drain resistance(Rd) can be obtained from the measured Z-parameters under zero bias condition. It is possible to define the new internal device including intrinsic device and 3 parasitic resistances by elimination the parasitic inductances and capacitances from the measured S-parameters. Three parasitic resistances are calculated easily from the fact that the real parts of Yint,11 and Yint,12 of intrinsic Y-parameters are zero theoretically and the relations between S-,Z-, Y-matrices. The calculated parasitic resistances using the presented method and successively calculated equivalent circuit parameters give modeled S-parameters which are in good agreement with the measured S-parameters up to 400Hz.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.11
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• pp.25-31
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• 2016

Parasitic capacitance and resistance of FinFET transistors are the important components that determine the frequency performance of the circuit. Therefore, the researchers in our group developed more accurate parasitic capacitance and resistance for FinFETs than BSIM-CMG. To verify the RF performance, proposed model was applied to design an LNA that has $S_{21}$ more than 10dB and center frequency more than 60GHz using HSPICE. To verify the accuracy of the proposed model, mixed-mode capability of 3D TCAD simulator Sentaurus was used. $S_{21}$ of LNA was chosen as a reference to estimate the error. $S_{21}$ of proposed model showed 87.5% accuracy compared to that of Sentaurus in 10GHz~100GHz frequency range. The $S_{21}$ accuracy of BSIM-CMG model was 56.5%, so by using the proposed model, the accuracy of the circuit simulator improved by 31%. This results validates the accuracy of the proposed model in RF domain and show that the accuracies of the parasitic capacitance and resistance are critical in accurately predicting the LNA performance.

• Proceedings of the IEEK Conference
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• 2009.05a
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• pp.85-87
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• 2009

This paper presents a new PID controller for a DC/DC boost converter model that has a parasitic inductor resistance. In order to maintain the robust output regulation property under load variations the proposed controller is designed by using an additional state variable developed via a parallel-damped passivity-based control approach. Simulation results using Matlab/Simulink SimPowerSystems compare the performances of the proposed controller with a conventional PI controller for reference step changes and load uncertainties.

• Korean Journal of Metals and Materials
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• v.50 no.10
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• pp.785-792
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• 2012

A new flip chip structure consisting of interlocking joints locally surrounded by non-conductive adhesive was investigated in order to improve the contact resistance characteristics and prevent the parasitic capacitance increase. The average contact resistance of the interlocking joints was substantially reduced from $135m{\Omega}$ to $79m{\Omega}$ by increasing the flip chip bonding pressure from 85 MPa to 185 MPa. Improvement of the contact resistance characteristics at higher bonding pressure was attributed not only to the increased contact area between Cu chip bumps and Sn pads, but also to the severe plastic deformation of Sn pads caused during formation of the interlocking-joint structure. The parasitic capacitance increase due to the non-conductive adhesive locally surrounding the flip chip joints was estimated to be as small as 12.5%.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.11
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• pp.49-54
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• 1990

In this paper, a simple model is presented for the gate-voltage dependence of the parasitic resistance in MOSFETs with the lightly-doped drain (LDD) structure. At the LDD region located under the gate electrode, an accumulation layer is formed due to the gate voltage. The parasitic resistance of the source side LDD in the channel is treated as a parallel combination of the resistance of the accumulation layer and that of the bulk LDD, which is approximated as a spreading resistance from the end of the channel inversion layer to the ${n^+}$/LDD junction boundary. Also the effects of doping gradients at the junction are discussed. As result of the model, the LDD resistance decreases with increasing the gate voltage at the linear regime, and increase quasi-linearly with the gate voltage at the saturation regime, considering th velocity saturation both in the channel and in the LDD region. The results are in good agreement with experimental data reported by others.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.50 no.8
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• pp.387-393
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• 2001

This paper describes an advanced measuring method and precise evaluation of the ground resistance for the grounding system of energized substations and power equipments. A grounding system of substations consists of all interconnected grounding connections of grounded conductors, neutral ground wires, underground conductors of distribution lines, cable shields, grounding terminals of equipments, and etc. It is very difficult to measure the accurate ground resistance of the grounding terminals of equipments, and etc. It is very difficult to measure the accurate ground resistance of the grounding system of high voltage energized substations because of harmonic components caused by switched power supplies or overloads. The conventional fall-of-potential method may be subject to big error if stray ground currents and potentials are present. In this work, to improve the precision in measurements of the ground resistance by eliminating the effects of harmonic components and stray currents and potentials, the investigations of the ground resistance measurement by using a low pass filter in a model energized grounding system were conducted. The accuracy of ground resistance mesurements was evaluated as a function of the ratio of the test signal to noise (S/N). The errors due to the proposed ground resistance measurement method were decreased with increasing S/N and were less than 5[%] as S/N is 10. The proposed ground resistance measurement method appears to be considerably more accurate than the conventional fall-of -potential method. It is allows cancellation of the parasitic resistance of energized grounding systems, to employ the measurement method that allows cancellation of the parasitic effects due to other circulating ground currents and ground potential rises in practical situations.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.312-317
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• 2015

In this paper, the RF characteristics of multi-finger MOSFETs were improved by decreasing the parasitic capacitance in spite of increased gate resistance in a 90-nm CMOS technology. Two types of device structures were designed to compare the parasitic capacitance in the gate-to-source ($C_{gs}$) and gate-to-drain ($C_{gd}$) configurations. The radio frequency (RF) performance of multi-finger MOSFETs, such as cut-off frequency ($f_T$) and maximum-oscillation frequency ($f_{max}$) improved by approximately 10% by reducing the parasitic capacitance about 8.2% while maintaining the DC performance.