• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.10
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• pp.1664-1671
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• 2016

This paper presents the analysis of the gate-source voltage of the gallium nitride high electronic mobility transistor (GaN HEMT) in the half bridge structure focused on the mutual effects of two switching operation. Especially low side gate-source voltage is analyzed mathematically according to the high side switch turn-on and turn-off operation. Moreover, the influence of each gate resistance and parasitic component on the switching characteristic of other side switch is investigated, and the formula, simulation and experimental results are compared with theoretical data.

• Transactions of the Society of Information Storage Systems
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• v.8 no.1
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• pp.16-21
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• 2012

SAW device is widely used as filters, sensors, actuators in various technologies. And capacitive sensor is tremendously used to measure pressure, gap, etc. The application of SAW device as signal conditioner of capacitive sensor reduces noise level and enables high precision measurement. The response increase of SAW based capacitive sensor is produced just before the two capacitive electrode contacts by the existence of parasitic resistance of capacitive electrode. In this paper, we analyze the effects of parasitic resistance and propose the calibrating method using lumped component and execute the high precision gap measurement using calibrated system. And xx nm resolution and yy ${\mu}m$ stroke was attained.

• Journal of Advanced Navigation Technology
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• v.15 no.4
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• pp.596-601
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• 2011

This paper has presented research results for the switching mode class E frequency multiplier that has simple circuit structure and high efficiency. Frequency multiplication is coming from the nonlinearity of the active component, and this paper models the FET active component as a simple switch and some parasitics to analyze the characteristics. The matching component parameters for the class E frequency doubler have been derived with modeling the FET as a input controlled switch and some parasitics. A circuit simulator, ADS, is used to simulate the output voltage and current waveform and efficiency with the variation of the parasitic values. With 2.9GHz input and 2V bias, the drain efficiency has been decreased from 98% to 28% with changing the parasitic capacitance from 0pF to 1pF at 5.8GHz output, which shows that the parasitic capacitance CP has the most significant effect on the efficiency among the parasitics of FET.

• Journal of Power Electronics
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• v.19 no.2
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• pp.591-601
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• 2019

With the development of renewable energy, grid-connected inverter technology has become an important research area. When compared with traditional silicon IGBT power devices, the silicon carbide (SiC) MOSFET shows obvious advantages in terms of its high-power density, low power loss and high-efficiency power supply system. It is suggested that this technology is highly suitable for three-phase AC motors, renewable energy vehicles, aerospace and military power supplies, etc. This paper focuses on the SiC MOSFET behaviors that concern the parasitic component influence throughout the whole working process, which is based on a three-phase grid-connected inverter. A high-speed model of power switch devices is built and theoretically analyzed. Then the power loss is determined through experimental validation.

• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.367-372
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• 1999

In this paper, an inverter fed induction motor drive system is analyed in order to predict the conducted interference. High frequency model for inverter, motor and system parasitic components are proposed. High frequency component allows time and frequency domain analysis to be performed with standard PSpice tool. The overall high frequency component and model are verified by comparing simulation and experimental result.

• ETRI Journal
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• v.15 no.3
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• pp.61-69
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• 1994

A new analytical model for the base current of Si/SiGe/Si heterojunction bipolar transistors(HBTs) has been developed. This model includes the hole injection current from the base to the emitter, and the recombination components in the space charge region(SCR) and the neutral base. Distinctly different from other models, this model includes the following effects on each base current component by using the boundary condition of the excess minority carrier concentration at SCR boundaries: the first is the effect of the parasitic potential barrier which is formed at the Si/SiGe collector-base heterojunction due to the dopant outdiffusion from the SiGe base to the adjacent Si collector, and the second is the Ge composition grading effect. The effectiveness of this model is confirmed by comparing the calculated result with the measured plot of the base current vs. the collector-base bias voltage for the ungraded HBT. The decreasing base current with the increasing the collector-base reverse bias voltage is successfully explained by this model without assuming the short-lifetime region close to the SiGe/Si collector-base junction, where a complete absence of dislocations is confirmed by transmission electron microscopy (TEM)[1].The recombination component in the neutral base region is shown to dominate other components even for HBTs with a thin base, due to the increased carrier storage in the vicinity of the parasitic potential barrier at collector-base heterojunction.

• Parasites, Hosts and Diseases
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• v.45 no.3
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• pp.165-174
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• 2007

Toxoplasma gondii GRA10 expressed as a GFP-GRA10 fusion protein in HeLa cells moved to the nucleoli within the nucleus rapidly and entirely. GRA10 was concentrated specifically in the dense fibrillar component of the nucleolus morphologically by the overlap of GFP-GRA10 transfection image with IFA images by monoclonal antibodies against GRA10 (Tg378), B23 (nucleophosmin) and C23 (nucleolin). The nucleolar translocalization of GRA10 was caused by a putative nucleolar localizing sequence (NoLS) of GRA10. Interaction of GRA10 with TATA-binding protein associated factor 1B (TAF1B) in the yeast two-hybrid technique was confirmed by GST pull-down assay and immunoprecipitation assay. GRA10 and TAF1B were also co-localized in the nucleolus after co-transfection. The nucleolar condensation of GRA10 was affected by actinomycin D. Expressed GFP-GRA10 was evenly distributed over the nucleoplasm and the nucleolar locations remained as hollows in the nucleoplasm under a low dose of actinomycin D. Nucleolar localizing and interacting of GRA10 with TAF1B suggested the participation of GRA10 in rRNA synthesis of host cells to favor the parasitism of T. gondii.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.26 no.11
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• pp.48-53
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• 2012

In this paper designed J-class amplifier that have high efficiency using parasitic of pHEMT. Measured results of the designed J-class amplifier is maxmum output power of 31.5dBm and gain of 16.5dB, minimum output power of 29.8dBm. when input power 15dBm. Maxmum drain efficiency is 76.2% at 2.95GHz, maxmum drain efficiency is 61%. The J-class amplifier has average gain of 15.35dB and average efficiency of 35%.

• Proceedings of the IEEK Conference
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• 2002.06e
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• pp.303-306
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• 2002

The EMI filter used in switching apparatus is designed on the basis of personal designer experience. A try and error approach leads to a considerables waste of time without assurance to come out to a good solution. The difficulty in the right choice of the component values resides on the dominant role played by their parasitic components at high frequencies and is aggravated by the poor knowledge of the internal impedance of the noise generators. In this paper, we proposed the design technique for the EMI filter effectively using the LISN and the EMI analyzer in the industrial field.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.89-92
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• 2001

In this paper, a simple low-power CMOS current reference circuit is proposed. The reference circuit includes parasitic pnp BJTs and resistors. Temperature compensation is made by adding a current component proportional to a thermal voltage to a current component proportional to a base-to-emitter voltage. The designed circuit has been simulated using a 0.25${\mu}{\textrm}{m}$ n-well CMOS process parameters. The simulation results show that the reference current is 34.96$mutextrm{A}$$\pm$0.04$mutextrm{A}$ in the temperature range of -2$0^{\circ}C$ to 12$0^{\circ}C$ The reference current varies less than 0.6% when the power supply voltage changes from 2.5V to 3.5V For $V_{DD=5V}$ and T=3$0^{\circ}C$ the power consumption is 520㎼ during normal operation but reduces to 0.l㎻ during power-down mode.