• Title/Summary/Keyword: Parallel-Addition

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Non-Contact Power Supply Using the Series-Parallel Resonant Converter (직ㆍ병렬 공진형 컨버터를 이용한 비접촉전원)

  • Kong Young-Su;Kim Eun-Soo;Yang Seung-Chul;Kim Jong-Mu;Shin Byung-Chul
    • The Transactions of the Korean Institute of Power Electronics
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    • v.9 no.5
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    • pp.405-412
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    • 2004
  • In this paper, Non-contact power supply(NCPS) with the long primary cable longer than 20m and the large air-gap between the primary and secondary of Non-Contacting Transformer(NCT) is presented. The NCT has a large leakage inductance bigger than its magnetizing inductance because it has low coupling, and it is not efficient for NCPS to transfer the primary energy to the secondary one. In order to improve this problem, the voltage-gain characteristics of the series resonant converter, the parallel resonant converter, and the series-parallel resonant converter are analyzed respectively. In addition, the experimental results of 10kW prototype the series-parallel resonant converter is presented.

Electrical power analysis of piezoelectric energy harvesting circuit using vortex current (와류를 이용한 압전 에너지 수확 회로의 전력 분석)

  • Park, Geon-Min;Lee, Chong-Hyun;Cho, Cheeyoung
    • The Journal of the Acoustical Society of Korea
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    • v.38 no.2
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    • pp.222-230
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    • 2019
  • In this paper, the power of the energy harvesting circuit using the PVDF (Polyvinylidene fluoride) piezoelectric sensor transformed by vortex was analyzed. For power analysis, a general bridge diode rectifier circuit and a P-SSHI (Parallel Synchronized Switch Harvesting on Inductor) rectifier circuit with a switching circuit were used. The P-SSHI circuit is a circuit that incorporates a parallel synchronous switch circuit at the input of a general rectifier circuit to improve energy conversion efficiency. In this paper, the output power of general rectifier circuit and P-SSHI rectifier circuit is analyzed and verified through theory and experiment. It was confirmed that the efficiency was increased by 69 % through the experiment using the wind. In addition, a circuit for storing the harvested energy in the supercapacitor was implemented to confirm its applicability as a secondary battery.

A comparative study on the addition architecture of high-speed checksum module (고속 검사합 모듈의 덧셈구조에 관한 비교 연구)

  • 김대현;한상원공진흥
    • Proceedings of the IEEK Conference
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    • 1998.10a
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    • pp.1029-1032
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    • 1998
  • In this paper, a comparative study is presented to evaluate the addition architecture of the high-speed checksum module in TCP/IP processing. In order to speed up TCP/IP processing, H/W implementation offers concurrent and parallel processing to yield high speed computation, with respect to S/W implementation. This research aims at comparing two addition architectures of checksum module, which is the major botteleneck in TCP/IP processing. The 16-bit and 8-bit byte-by-byte addition architecture are implemented by the full custom design, and compared, in analytical and experimental manner, from standpoint of space and performance. For LG $0.6\mu\textrm{m}$ TLM process, the 8-bit addition implementation requires the area, 1.3 times larger than the 16-bit one, and it operates at 80MHz while the 16-bit one runs by 66MHz.

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Line Impedance Estimation Based Adaptive Droop Control Method for Parallel Inverters

  • Le, Phuong Minh;Pham, Xuan Hoa Thi;Nguyen, Huy Minh;Hoang, Duc Duy Vo;Nguyen, Tuyen Dinh;Vo, Dieu Ngoc
    • Journal of Power Electronics
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    • v.18 no.1
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    • pp.234-250
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    • 2018
  • This paper presents a new load sharing control for use between paralleled three-phase inverters in an islanded microgrid based on the online line impedance estimation by the use of a Kalman filter. In this study, the mismatch of power sharing when the line impedance changes due to temperature, frequency, significant differences in line parameters and the requirements of the Plug-and-Play mode for inverters connected to a microgrid has been solved. In addition, this paper also presents a new droop control method working with the line impedance that is different from the traditional droop algorithm when the line impedance is assumed to be pure resistance or pure inductance. In this paper, the line impedance estimation for parallel inverters uses the minimum square method combined with a Kalman filter. In addition, the secondary control loops are designed to restore the voltage amplitude and frequency of a microgrid by using a combined nominal value SOGI-PLL with a generalized integral block and phase lock loop to monitor the exact voltage magnitude and frequency phase at the PCC. A control model has been simulated in Matlab/Simulink with three voltage source inverters connected in parallel for different ratios of power sharing. The simulation results demonstrate the accuracy of the proposed control method.

An Effective Parallel Implementation of Sound Synthesis of Guitar using GPU (GPU를 이용한 기타의 음 합성을 위한 효과적인 병렬 구현)

  • Kang, Sung-Mo;Kim, Jong-Myon
    • Journal of the Korea Society of Computer and Information
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    • v.18 no.8
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    • pp.1-8
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    • 2013
  • This paper proposes an effective parallel implementation of a physical modeling synthesis of guitar on the GPU environment. We used appropriate filter coefficients and adjusted the length of delay line for each open string to generate 44,100 six-polyphonic guitar sounds (E2, A2, D3, G4, B3, E4) by using physical modeling synthesis. In addition, we analyzed the physical modeling synthesis algorithm and observed that we can exploit parallelism inherent in the length of delay line. Thus, we assigned CUDA cores as many as the length of delay line and effectively implemented the physical modeling synthesis using GPU to achieve the highest performance. Experimental results indicated that synthetic guitar sounds using GPU were very similar to the original sounds when we compared their spectra. In addition, GPU achieved 68x and 3x better performance than high-performance TI DSP and CPU, respectively. Furthermore, this paper implemented and evaluated the performance of multi-GPU systems for the physical modeling algorithm.

A Study on PV AC-Module with Active Power Decoupling and Energy Storage System

  • Won, Dong-Jo;Noh, Yong-Su;Lim, Hong-Woo;Won, Chung-Yuen
    • Journal of Power Electronics
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    • v.16 no.5
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    • pp.1894-1903
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    • 2016
  • In general, electrolytic capacitors are used to reduce power pulsations on PV-panels. However, this can reduce the reliability of the PV AC-module system, because electrolytic capacitors have a shorter lifetime than PV-panels. In addition, PV-panels generate irregular power and inject it into the grid because the output power of a PV-panel depends on the surrounding conditions such as irradiation and temperature. To solve these problems, a grid-connected photovoltaic (PV) AC-module with active power decoupling and energy storage is proposed. A parallel bi-directional converter is connected to the AC module to reduce the output power pulsations of PV-panels. Thus, the electrolytic capacitor can be replaced with a film capacitor. In addition, the irregular output power due to the surrounding conditions can be regulated by using a parallel energy storage circuit. To maintain the discontinuous conduction mode at low irradiation, the frequency control method is adopted. The design method of the proposed converter and the operation principles are introduced. An experimental prototype rated at 125W was built to verify the performance of the proposed converter.

An Efficient Parallel Testing using The Exhaustive Test Method (Exhaustive 테스트 기법을 사용한 효율적 병렬테스팅)

  • 김우완
    • Journal of KIISE:Computer Systems and Theory
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    • v.30 no.3_4
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    • pp.186-193
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    • 2003
  • In recent years the complexity of digital systems has increased dramatically. Although semiconductor manufacturers try to ensure that their products are reliable, it is almost impossible not to have faults somewhere in a system at any given time. As complexity of circuits increases, the necessity of more efficient organized and automated methods for test generation is growing. But, up to now, most of popular and extensive methods for test generation nay be those which sequentially produce an output for an input pattern. They inevitably require a lot of time to search each fault in a system. In this paper, corresponding test patterns are generated through the partitioning method among those based on the exhaustive method. In addition, the method, which can discovers faults faster than other ones that have been proposed ever by inserting a pattern in parallel, is designed and implemented.

Analysis of the Redundant Actuation Characteristics of the Planar 3-DOF Parallel Mechanism (평면형 3자유도 병렬 메커니즘의 여유 구동 특성 분석)

  • Jeon, Jung In;Oh, Hyun Suk;Woo, Sang Hun;Kim, Sung Mok;Kim, Min Gun;Kim, Whee Kuk
    • The Journal of Korea Robotics Society
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    • v.12 no.2
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    • pp.194-205
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    • 2017
  • A redundantly actuated planar 3-degree-of-freedom parallel mechanism is analyzed to show its high application potential as a haptic device. Its structure along with the closed form forward position solutions is briefly discussed. Then its geometric and kinematic characteristics via singularity analysis, the kinematic isotropy index, and the input-output force transmission ratio are investigated both for the redundantly actuated cases and for the non-redundantly actuated case. In addition, comparative joint torque simulations of the mechanism with different number of redundant actuations as well as without redundant actuation are conducted to confirm the improved joint torque distribution characteristics. Through these analyses it is shown that the geometric and kinematic characteristics of the redundantly actuated mechanism are superior to the ones of the mechanism without redundant actuation. Thus, it can be concluded that the suggested planar mechanism with redundant actuation has a very high potential for haptic device applications.

A Study on the Evaluation of Air Change Efficiency of Multi-Air-Conditioner with Ventilation System for Heating Season (환기시스템이 적용된 히트펌프의 난방시 급기효율 평가에 관한 연구)

  • Kwon Yong-Il;Han Hwataik;Kim Kyung-Hwan;Chung Baik-Young;Lee Gam-Gue
    • Korean Journal of Air-Conditioning and Refrigeration Engineering
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    • v.17 no.1
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    • pp.56-61
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    • 2005
  • Indoor air quality becomes of a concern recently in view of human health. This study investigates the air diffusion performance and the air change efficiency of a classroom, when outdoor air is introduced in addition to the heating/cooling operation of a ceiling-mounted heat pump. A CFD analysis has been performed to investigate the effect of the discharge angle of the air jets from the heat pump for both parallel and series types of outdoor air system. It is observed that the series type creates more uniform indoor environment compared to the parallel type in general. It can be concluded the discharge angle should not be larger than 40o for the parallel type, in order not to generate thermal stratification in the room.

A linear array SliM-II image processor chip (선형 어레이 SliM-II 이미지 프로세서 칩)

  • 장현만;선우명훈
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.35C no.2
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    • pp.29-35
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    • 1998
  • This paper describes architectures and design of a SIMD type parallel image processing chip called SliM-II. The chiphas a linear array of 64 processing elements (PEs), operates at 30 MHz in the worst case simulation and gives at least 1.92 GIPS. In contrast to existing array processors, such as IMAP, MGAP-2, VIP, etc., each PE has a multiplier that is quite effective for convolution, template matching, etc. The instruction set can execute an ALU operation, data I/O, and inter-PE communication simulataneously in a single instruction cycle. In addition, during the ALU/multiplier operation, SliM-II provides parallel move between the register file and on-chip memory as in DSP chips, SliM-II can greatly reduce the inter-PE communication overhead, due to the idea a sliding, which is a technique of overlapping inter-PE communication with computation. Moreover, the bandwidth of data I/O and inter-PE communication increases due to bit-parallel data paths. We used the COMPASS$^{TM}$ 3.3 V 0.6.$\mu$m standrd cell library (v8r4.10). The total number of transistors is about 1.5 muillions, the core size is 13.2 * 13.0 mm$^{2}$ and the package type is 208 pin PQ2 (Power Quad 2). The performance evaluation shows that, compared to a existing array processors, a proposed architeture gives a significant improvement for algorithms requiring multiplications.s.

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