• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.1
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• pp.106-113
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• 2003

In this paper, we proposed low noise amplifier for 2.4GHz ISM frequency with CMOS technology. The property of noise and gain is improved by cascode architecture. The architecture, which common source output of cascode is connected to input of parallel MOS, reduce IM. The LNA results based on Hynix 0.35${\mu}{\textrm}{m}$ 2poly 4metal CMOS processor with a 3.3V supply. It achieves a gain of 13dB, noise figure of 1.7dB, IP3 of 8dBm, Input/output matching of -31dB/-28dB, reverse isolation of -25dB. and power dissipation of 4.7mW with HSPICE simulation. The size of layout is smaller than 2 ${\times}$ 2mm with Mentor.

• Journal of Korea Multimedia Society
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• v.15 no.1
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• pp.81-86
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• 2012

This paper presents a VLSI design for lifting-based discrete wavelet transform (DWT) 9/7 filter using multiplierless multiple constant multiplication (MCM) architecture. This proposed design is based on the lifting scheme using pattern search for folded architecture. Shift-add operation is adopted to optimize the multiplication process. The conventional serial operations of the lifting data flow can be optimized into parallel ones by employing paralleling and pipelining techniques. This optimized design has simple hardware architecture and requires less computation without performance degradation. Furthermore, hardware utilization reaches 100%, and the number of registers required is significantly reduced. To compare our work with previous methods, we implemented the architecture using Verilog HDL. We also executed simulation based on the logic synthesis using $0.18{\mu}m$ CMOS standard cells. The proposed architecture shows hardware reduction of up to 60.1% and 44.1% respectively at 200 MHz clock compared to previous works. This implementation results indicate that the proposed design performs efficiently in hardware cost, area, and power consumption.

• Journal of Digital Convergence
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• v.13 no.12
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• pp.381-390
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• 2015

One of the fundamental requirements of entertainment applications is interactivity with users. The mobile device such as the smartphone, however, does not guarantee it due to the limit of the application processor's computing power, memory size and available electric power of the battery. This paper proposes a methodology to boost responsiveness of interactive applications by taking advantage of the parallel architecture of mobile devices which, for instance, have dual-core, quad-core or octa-core. To harness the multi-core architecture, it exploits the POSIX thread, a platform-independent thread library to be able to be used in various mobile platforms such as Android, iOS, etc. As a useful application example of the methodology, a heavy matrix calculation function was transformed to a parallelized version which showed around 2.5 ~ 3 times faster than the original version in a real-world usage environment.

• The KIPS Transactions:PartA
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• v.10A no.6
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• pp.627-634
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• 2003

In this paper, we consider a graph-theoretic problem,, the so-called "graph embedding problem" that maps the vertices and edges of the given guest graph model into the corresponding vertices and paths of the host graph under the condition of maintaining better performance parameters such as dilation, congestion, and expansion. We firstly propose a new mapping function which can embed the pyramid model with height N into the 3-dimensional mesh massively parallel processor system with the height $(4^{(N+1)/3}+2)/3$ and the regular 2-dimensional mesh of one side $2^{(2N-1)/3}$, and analyze the performance of the embedding in terms of the dilation parameter that reflects the number of communication steps between two adjacent vertices under the embedding. We prove that the dilation of the embedding is $2{\cdot}4^{(N-2)/3}+4)/3$. This is superior to the previous result of $4^{N+183}+2)/3$ under the same condition.condition.

• The KIPS Transactions:PartA
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• v.14A no.5
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• pp.301-308
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• 2007

This paper proposes high performance coprocessor architecture for real time dense disparity computation based on a phase-based binocular stereo matching technique called local weighted phase-correlation(LWPC). The algorithm combines the robustness of wavelet based phase difference methods and the basic control strategy of phase correlation methods, which consists of 4 stages. For parallel and efficient hardware implementation, the proposed architecture employs SIMD(Single Instruction Multiple Data Stream) architecture for each functional stage and all stages work on pipelined mode. Such that the newly devised pipelined linear array processor is optimized for the case of row-column image processing eliminating the need for transposed memory while preserving generality and high throughput. The proposed architecture is implemented with Xilinx HDL tool and the required hardware resources are calculated in terms of look up tables, flip flops, slices, and the amount of memory. The result shows the possibility that the proposed architecture can be integrated into one chip while maintaining the processing speed at video rate.

• Journal of Electrical Engineering and Technology
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• v.8 no.5
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• pp.1029-1039
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• 2013

To avoid undesirable disconnection of healthy wind generators (WGs) or a wind power plant, a WG protection relay should discriminate among faults, so that it can operate instantaneously for WG, connected feeder or connection bus faults, it can operate after a delay for inter-tie or grid faults, and it can avoid operating for parallel WG or adjacent feeder faults. A WG protection relay based on the positive- and negative-sequence fault components is proposed in the paper. At stage 1, the proposed relay uses the magnitude of the positive-sequence component in the fault current to distinguish faults requiring non-operation response from those requiring instantaneous or delayed operation responses. At stage 2, the fault type is first determined using the relationships between the positive- and negative-sequence fault components. Then, the relay differentiates between instantaneous operation and delayed operation based on the magnitude of the positive-sequence fault component. Various fault scenarios involving changes in position and type of fault and faulted phases are used to verify the performance of the relay. This paper concludes by implementing the relay on a hardware platform based on a digital signal processor. Results indicate that the relay can successfully distinguish the need for instantaneous, delayed, or non-operation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.10a
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• pp.499-503
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• 2000

The use of Multiple-Valued FFT(Fast fourier Transform) is extended from binary to multiple-valued logic(MVL) circuits. A multiple-valued FFT circuit can be implemented using current-mode CMOS techniques, reducing the transitor, wires count between devices to half compared to that of a binary implementation. For adder processing in FFT, We give the number representation using such redundant digit sets are called redundant positive-digit number representation and a Redundant set uses the carry-propagation-free addition method. As the designed Multiple-valued FFT internally using PD(positive digit) adder with the digit set 0,1,2,3 has attractive features on speed, regularity of the structure and reduced complexities of active elements and interconnections. for the mutiplier processing, we give Multiple-valued LUT(Look up table)to facilitate simple mathmatical operations on the stored digits. Finally, Multiple-valued 8point FFT operation is used as an example in this paper to illuatrates how a multiple-valued FFT can be beneficial.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.2
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• pp.11-19
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• 2015

Since CMOS device scaling has stalled, three-dimensional (3-D) integration allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. 3-D integration has many benefits such as increased multi-functionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, because it vertically stacks multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip. Anticipated applications start with memory, handheld devices, and high-performance computers and especially extend to multifunctional convengence systems such as cloud networking for internet of things, exascale computing for big data server, electrical vehicle system for future automotive, radioactivity safety system, energy harvesting system and, wireless implantable medical system by flexible heterogeneous integrations involving CMOS, MEMS, sensors and photonic circuits. However, heterogeneous integration of different functional devices has many technical challenges owing to various types of size, thickness, and substrate of different functional devices, because they were fabricated by different technologies. This paper describes new 3-D heterogeneous integration technologies of chip self-assembling stacking and 3-D heterogeneous opto-electronics integration, backside TSV fabrication developed by Tohoku University for multifunctional convergence systems. The paper introduce a high speed sensing, highly parallel processing image sensor system comprising a 3-D stacked image sensor with extremely fast signal sensing and processing speed and a 3-D stacked microprocessor with a self-test and self-repair function for autonomous driving assist fabricated by 3-D heterogeneous integration technologies.

• The Journal of Korean Association of Computer Education
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• v.11 no.3
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• pp.81-89
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• 2008

The failure occurrence of resources in the grid computing is higher than in a tradition parallel computing. Since the failure of resources affects job execution fatally, fault tolerance service is essential in computational grids. And grid services are often expected to meet some minimum levels of quality of service (QoS) for desirable operation. However Globus toolkit does not provide fault tolerance service that supports fault detection service and management service and satisfies QoS requirement. Thus this paper proposes fault tolerance service to satisfy QoS requirement in computational grids. In order to provide fault tolerance service and satisfy QoS requirements, we expand the definition of failure, such as process failure, processor failure, and network failure. And we propose resource scheduling service, fault detection service and fault management service and show implement and experiment results.

• Korea journal of population studies
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• v.23 no.2
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• pp.189-207
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• 2000

Focusing on the factors related to the amount of contact between young married women and their noncoresident parents and their noncoresident parents-in-law, the study hypothesized two scenarios. (1) filial piety scenario which predicts that the contact with one set of parents is not affected by accessibility of other set of parents, and (2) competition scenario which predicts that ease of contact with one set of parents inhibits contact with other set of parents. These scenarios were tested against the data from National Fertility and Family Health Survey in 1994. The regression analysis of intergenerational visits appeared to support the competition scenario : The parents-in-law and the parents seem to bs in competition for visits by young married women - distance from the parents from one side has a parallel relationship to more frequent visits with the other set of parents. This is a much more equal footing for both sides of the family than attention to filial piety would predict. although the level of support from the young generation may keep declining.