• 전기의세계
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• 제28권9호
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• pp.35-40
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• 1979

A grounded inductor is proposed which contains only one resistor and operational amplifier. The circuit uses the inherent frequency dependent characteristic of an amplifier to simulate the inductor. A parallel resonance circuit is constructed with the proposed circuit. It has been proved by the experimental results of the resonant circuit that the proposed circuit is equivalent to the grounded lossy inductor. The lossy inductor is imbedded in a passive bandstop prototype, and the resultant characteristic curve has been verified by the experiment.

• Journal of electromagnetic engineering and science
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• 제11권3호
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• pp.166-173
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• 2011

In this paper, we implemented and analyzed a wireless power transfer (WPT) system with a CSPR topology. CSPR refers to constant current source, series resonance circuit topology of a transmitting coil, parallel resonance circuit topology of a receiving coil, and pure resistive loading. The transmitting coil is coupled by a magnetic field to the receiving coil without wire. Although the electromotive force (emf) is small (about 4.5V), the voltage on load resistor is 148V, because a parallel resonance scheme was adopted for the receiving coil. The implemented WPT system is designed to be able to transfer up to 1 kW power and can operate a LED TV. Before the implementation, the EMF reduction mechanism based on the use of ferrite and a metal shield box was confirmed by an EM simulation and we found that the EMF can be suppressed dramatically by using this shield. The operating frequency of the implemented WPT system is 30.7kHz and the air gap between two coils is 150mm. The power transferred to the load resistor is 147W and the real power transfer efficiency is 66.4 %.

• Journal of Electrical Engineering and Technology
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• 제10권1호
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• pp.128-137
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• 2015

A novel parallel three-level zero voltage switching (ZVS) DC converter is presented for medium voltage applications. The proposed converter includes three sub-circuits connected in parallel with the same power switches to share load current and reduce the current stress of passive components at the output side. Thus, the size of the output chokes is reduced and the switch counts in the proposed converter are less that in the conventional parallel three-level DC/DC converter. Each sub-circuit combines one half-bridge converter and one three-level converter. The transformer secondary windings of these two converters are connected in series in order to reduce the size of output inductor. Due to the three-level circuit topology, the voltage stress of power switches is equal to $V_{in}/2$. Based on the resonant behavior by the output capacitance of power switches and the leakage inductance (or external inductance) at the transition interval, each switch can be turned on under ZVS. Finally, experiments based on a 2 kW prototype are provided to verify the performance of the proposed converter.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2008년도 춘계학술대회 논문집
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• pp.412-415
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• 2008

In a research on the practical dye-sensitized solar cell, a study on a large module have preference because module must be able to generate the proper current that is possible to convert electrically. So the parallel connection of dye-sensitized solar cells which outputs a large current easily is essential. However, there is a current loss in a paralle connection of dye-sensitized solar cells and the loss becomes larger according to increasing the number of parallel connection. In this study, we analyzed the cause of the current loss in the parallel connection by using the equivalent circuit analysis. One DSC used in this experiment had an active area $8cm^2$(4.62cm$\times$1.73cm) and it attained a conversion efficiency of 5.43% under 1 sun illumination ($P_{in}$ of 100 mW/$cm^2$) using a solar simulator.

• 한국정보과학회논문지:소프트웨어및응용
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• 제37권8호
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• pp.647-652
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• 2010

Esterel이라는 절차형(imperative) 동기(synchronous) 언어로부터 회로를 합성(synthesis)할 때, 하나의 동기장치(synchronizer)가 한 클럭에 중복사용되는 문제(schizophrenic parallel synchronizer)가 발생할 수 있다. 기존 컴파일러는 동기장치가 중복사용될 경우 동기장치를 복제하여 이 문제를 해결하고 있다. 본 논문은 동기장치가 중복사용되더라도 회로상/기능상 문제가 없는 조건을 제시하고, 이를 기반으로 소스코드를 분석하여 복제해야만 하는 동기장치를 찾아주는 알고리즘을 제안한다. 이 알고리즘은 컴파일러가 중복사용되는 동기장치들 중에서 꼭 복제해야만 하는 것을 알 수 있게 해 주어, Esterel 프로그램을 좀 더 작은 회로로 합성할 수 있도록 한다.

• 산업경영시스템학회지
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• 제29권2호
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• pp.7-12
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• 2006

This study considers the problem of scheduling jobs on uniform parallel machines with a common due date. The objective is to minimize the total absolute deviation of job completion times about the common due date. This problem is motivated by the fact that a certain phase of printed circuit board manufacturing is bottleneck and the processing speeds of parallel machines in this phase are uniformly different for all jobs. Optimal properties are proved and a simple polynomial time optimal algorithm is developed.

• 전자공학회논문지SC
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• 제43권5호
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• pp.36-43
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• 2006

본 논문에서는 $GF(2^m)$상에서 표준기저를 사용한 두 다항식의 승산을 비트-병렬로 실현하는 새로운 형태의 고속 병렬 승산기를 제안하였다. 승산기의 구성에 앞서, 피승수 다항식과 기약다항식의 승산을 병렬로 수행한 후 승수 다항식의 한 계수와 비트-병렬로 승산하여 결과를 생성하는 MOD 연산부를 구성하였다. MOD 연산부의 기본 셀은 2개의 AND 게이트와 2개의 XOR 게이트로 구성되며, 이들로부터 두 다항식의 비트-병렬 승산을 수행하여 승산결과를 얻도록 하였다. 이러한 과정을 확장하여 m에 대한 일반화된 회로의 설계를 보였으며, 간단한 형태의 승산회로 구성의 예를 $GF(2^4)$를 통해 보였다. 또한 제시한 승산기는 PSpice 시뮬레이션을 통하여 동작특성을 보였다. 본 논문에서 제안한 승산기는 기본 셀에 의한 MOD 연산부가 반복적으로 이루어짐으로서 차수 m이 매우 큰 유한체상의 두 다항식의 승산에서 확장이 용이하며, VLSI에 적합하다. 또한 승산기회로의 내부에 메모리 소자를 사용하지 않기 때문에 연산과정 중 소자에 의해 발생하는 지연시간이 적으므로 고속의 연산을 수행할 수 있다.

• Smart Structures and Systems
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• 제14권6호
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• pp.1131-1150
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• 2014

One of the issues in extending the range of applicable problems of real-time hybrid simulation is the computation speed of the simulator when large-scale computational models with a large number of DOF are used. In this study, functionality of real-time dynamic simulation of MDOF systems is achieved by creating a logic circuit that performs the step-by-step numerical time integration of the equations of motion of the system. The designed logic circuit can be implemented to an FPGA-based system; FPGA (Field Programmable Gate Array) allows large-scale parallel computing by implementing a number of arithmetic operators within the device. The operator splitting method is used as the numerical time integration scheme. The logic circuit consists of blocks of circuits that perform numerical arithmetic operations that appear in the integration scheme, including addition and multiplication of floating-point numbers, registers to store the intermediate data, and data busses connecting these elements to transmit various information including the floating-point numerical data among them. Case study on several types of linear and nonlinear MDOF system models shows that use of resource sharing in logic synthesis is crucial for effective application of FPGA to real-time dynamic simulation of structural response with time step interval of 1 ms.

• 한국초전도ㆍ저온공학회논문지
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• 제14권3호
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• pp.13-17
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• 2012

KEPCO Research Institute has been researching a Superconducting Fault Current Limiter (SFCL) which is considered one of solutions of fault current problems with Korea Institute of Machinery & Materials (KIMM) and Hanyang University since 2011. In this paper, we fabricated a current limiting module and conducted electrical short circuit tests for checking the validity of the transmission level SFCL design. Based on the short circuit characteristics of the second generation High Temperature Superconductor (HTS), we analyzed the short circuit characteristics of 3 parallel connected superconducting wires. The structure of the HTS wire is as follows: the stainless steel stabilizer of $100{\mu}m$ is laminated on the superconductor layer and under the substrate, both of which are electrically jointed with solder. We fabricated the current limiting module which has 40 series and 6 parallel connections and studied the short circuit characteristics of the module under various voltage levels.

• 대한설비공학회:학술대회논문집
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• 대한설비공학회 2007년도 동계학술발표대회 논문집
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• pp.216-221
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• 2007

An experiment was carried out to investigate the effect of a coolant circuit arrangement on the heat transfer and air pressure drop of a fin-tube sensible heat exchanger with the corrugated fin surface. The air inlet temperature was set to $23^{\circ}C$,the relative humidity to 50% and the air inlet flow rate to 20, 22, $25m^3/min$, respectively. while the coolant temperature was set to $7^{\circ}C$, and the coolant mass flow rate to 10, 16, 22kg/min, respectively. Experiment showed that the exchanger having a diameter of 12.7mm with parallel circuit does better performance in sensible heat transfer and air pressure drop than those three of diameter of 12.7mm with a series circuit and that with diameter of 15.88mm with a parallel circuit.