• KIPS Transactions on Computer and Communication Systems
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• v.10 no.9
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• pp.243-250
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• 2021

Recently, with the development of cloud computing, interest in database outsourcing is increasing. However, when the database is outsourced, there is a problem in that the information of the data owner is exposed to internal and external attackers. Therefore, in this paper, we propose a parallel range query processing algorithm that supports privacy protection. The proposed algorithm uses the Paillier encryption system to support data protection, query protection, and access pattern protection. To reduce the operation cost of a checking protocol (SRO) for overlapping regions in the existing algorithm, the efficiency of the SRO protocol is improved through a garbled circuit. The proposed parallel range query processing algorithm is largely composed of two steps. It consists of a parallel kd-tree search step that searches the kd-tree in parallel and safely extracts the data of the leaf node including the query, and a parallel data search step through multiple threads for retrieving the data included in the query area. On the other hand, the proposed algorithm provides high query processing performance through parallelization of secure protocols and index search. We show that the performance of the proposed parallel range query processing algorithm increases in proportion to the number of threads and the proposed algorithm shows performance improvement by about 5 times compared with the existing algorithm.

• Journal of International Academy of Physical Therapy Research
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• v.6 no.2
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• pp.902-907
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• 2015

The purpose of this study was to parallel circuit training and circuit training with sonic systemic mechanism was to compare the differences in pulmonary function and chest expansion in adult men. This study was performed on 20 subjects. 20 subjects were divided into two groups; Circuit training group(n=10), Circuit training with sonic systemic mechanism(n=10). Both of the group performed the exercise 3 times a week for 5 weeks. The data was analyzed by the Repeated t-test for comparing before, during and after changes of factors in each group and the Independent t-test for comparing the between groups. The result are as follows. Circuit training group was statistically significant difference FVC, FEV1/FVC(p<.05), Circuit training with sonic systemic mechanism group was statistically significant difference PEF, VC in pulmonary function(p<.05). Circuit training group was statistically significant difference FEV1/FVC of between the two group in pulmonary function(p<.05). Circuit training group and circuit training with sonic systemic mechanism group was statistically significant difference in chest expansion(p<0.05) and there was no statistically significant difference of between the two group in chest expansion(p>.05).

• Journal of electromagnetic engineering and science
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• v.8 no.2
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• pp.47-51
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• 2008

In this paper, we present a cost effective parallel-branch spiral inductor with the enhanced quality factor and the resonance frequency. This structure is designed to improve the quality factor, but different from other fully stacked spiral inductors. The parallel-branch effect is increased by overlapping the first metal below the second metal with same direction. Measurement result shows an increased quality factor of 12 % improvement. Also, we show an octagonal parallel-branch inductor which reduces the parasitic capacitances for higher frequency applications.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.6
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• pp.738-744
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• 2018

This paper proposes a low cost hot swap operation circuit of a parallel operation power supply for servers. Hot swap function for server power system is essential in 24 hour operation system such as internet data center, server, factory and etc. Server power supplies used in internet data centers have two or more parallel operations with the hot swap operation. However, the cost of the power supply is high because the controller IC for hot swap operation is very expensive. Therefore, this paper proposes a parallel-operated power supply with a low-cost hot swap controller for servers. The proposed system can operate hot swap function by using discrete devices and reduce the cost by more than 50%. A 1.2kW prototype system is implemented to verify the proposed low cost hot swap controller.

• Smart Structures and Systems
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• v.25 no.4
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• pp.423-432
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• 2020

In this paper, a novel but practical approach named series/parallel multi-sensing technique was proposed to evaluate the bolt looseness in a bolt group. The smart washers (SWs), which were fabricated by embedding a Lead Zirconate Titanate (PZT) transducer into two flat metal rings, were installed to the bolts group. By series connection of SWs, the impedance signals of different bolts can be obtained through only one sweep. Therefore, once the loosening occurred, the shift of different peak frequencies can be used to locate which bolt has loosened. The proposed multi input single output (MISO) damage detection scheme is very suitable for the structural health monitoring (SHM) of joint with a large number of bolts connection. Another notable contribution of this paper is the proposal of 3-dB bandwidth root mean square deviation (3 dB-RMSD) which can quantitatively evaluate the severity of bolt looseness. Compared with the traditional naked-eye observation method, the equivalent circuit based 3-dB bandwidth can accurately define the calculation range of RMSD. An experiment with three bolted connection specimens that installed the SWs was carried out to validate our proposed approach. Experimental result shows that the proposed 3 dB-RMSD based multi-sensing technique can not only identify the loosened bolt but also monitor the severity of bolt looseness.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.2 s.93
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• pp.167-173
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• 2005

The isolation of the series PIN diode switch is restricted by the parallel capacitance of PIN diode and the switch driver circuit limits switching speed of PIN diode switch. To overcome these problems, a high isolation and high switching speed Pin diode switch is proposed adapting the parallel resonant inductance and TTL compatible switch driver circuit. The measurement results of the 3 GHz PM diode switch show 1 GHz frequency band, less than 1.5 dB insertion loss, 65 dB isolation, more than 15 dB return loss and less than 30 ns switching speed. In particular the 3 GHz PIN diode switch using the parallel resonant inductance exhibits the improvement of isolation by 15 dB.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.277-278
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• 2005

Admittance Spectroscopic analysis was applied to study the effect of LiF buffer layer and to model the equivalent circuit for poly(2-methoxy-5-(2'-ethylhexyloxy)-1,4-phenylenevinylene) (MEH-PPV)-based polymer light emitting diodes (PLEDs) with the LiF cathode buffer layer. The single layer device with ITO/MEH-PPV/Al structure can be modeled as a simple parallel combination of resistor and capacitor. Insertion of a LiF layer at the Al/MEH-PPV interface shifts the highest occupied molecular orbital level and the vacuum level of the MEH-PPV layer as a result the barrier height for electron injection at the Al/MEH-PPV interface is reduced. The admittance spectroscopy measurement of the devices with the LiF cathode buffer layer shows reduction in contact resistance ($R_c$), parallel resistance ($R_p$) and increment in parallel capacitance ($C_p$).

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.3
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• pp.62-68
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• 1996

A CMOS transmitter ASIC for the ATM switching system etc., was designed to transmit 155.52 Mbps serial data transformed from 19.44 Mbps parallel data. 155.52 MHz clock for synchronization of data is genrated using reference 19.44 MHz clock by an analog PLL while parallel to serial data conversion is done by a digital circuit. Circuit simulations confirm that PLL locking and data conversion are accomplished successfully. The area of the designed ASIC chip is 1.3${\times}1.0mm^2$. The locking time and the power consumption of the chip are about 600 nsec and less than 150 mW, respectively.

• Proceedings of the KIEE Conference
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• 1994.07a
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• pp.525-527
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• 1994

A quasi parallel resonant do-link (QPRDCL) circuit with improved PWM capability is Proposed for tile zero voltage switching (ZVS) three phase PWM inverter. The peak voltage stresses of switches are all clamped to the dc-link voltage $V_d$. The proposed QPRDCL inverter has highly improved PWM capability due to selecting the on/off instants of the resonant link at will. Operational principles and analyses of the proposed QPRDCL circuit are explained and verified by simulation results.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1573-1576
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• 1987

A 4-bit parallel-series A/D converter has been designed using a new matrix circuit and breadboarded with transister array(TPQ2483). The simple matrix circuit is substituted for D/A converter and sebtracter-multiplier. The system has been simulated with SPICE. This converter is capable of operating at clock rate of 20MHz.