• The KIPS Transactions:PartC
• /
• v.19C no.4
• /
• pp.247-252
• /
• 2012

Network coding has been shown to improve various performance metrics in network systems. However, if network coding is implemented as software a huge time delay may be incurred at encoding/decoding stage so it is imperative for network coding to be parallelized to reduce time delay when encoding/decoding. In this paper, we compare the performance of parallelized decoders for random linear network coding (RLC) and pipeline network coding (PNC), a recent development in order to alleviate problems of RLC. We also compare multi-threaded algorithms on multi-core CPUs and massively parallelized algorithms on GPGPU for PNC/RLC.

• Journal of IKEEE
• /
• v.10 no.2 s.19
• /
• pp.128-133
• /
• 2006

This paper describes a high speed interface circuit using redundant multi-valued logic for high speed communication ICs. This circuit is composed of encoding circuit that serial binary data are received and converted into parallel redundant multi-valued data, and decoding circuit that converts redundant multi-valued data to parallel binary data. Because of the multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, the proposed 1:4 DEMUX (demultiplexer, serial-parallel converter), was designed using a 0.35um standard CMOS technology. Proposed DEMUX is achieved an operating speed of 4.5Gb/s with a supply voltage of 3.3V and with power consumption of 53mW. The operating speed of this circuit is limited by the maximum frequency which the 0.35um process has. Therefore, this circuit is to achieve CMOS communication ICs with an operating speed greater than 10Gb/s in submicron process of high operating frequency.

• Korean Journal of Optics and Photonics
• /
• v.24 no.5
• /
• pp.262-270
• /
• 2013

In this paper, we propose a modified optical CBC(Cipher Block Chaining) encryption method using optical XOR logic operations. The proposed method is optically implemented by using dual encoding and a free-space interconnected optical logic gate technique in order to process XOR operations in parallel. Also, we suggest a CBC encryption/decryption optical module which can be fabricated with simple optical architecture. The proposed method makes it possible to encrypt and decrypt vast two-dimensional data very quickly due to the fast optical parallel processing property, and provides more security strength than the conventional electronic CBC algorithm because of the longer security key with the two-dimensional array. Computer simulations show that the proposed method is very effective in CBC encryption processing and can be applied to even ECB(Electronic Code Book) mode and CFB(Cipher Feedback Block) mode.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.41 no.2
• /
• pp.163-171
• /
• 2016

In order to detect the exact position of high-speed train, it is necessary to obtain location information from the transponder tag installed along the track. In this paper, we proposed parallel descrambling scheme for high-speed railway transponder system, which aims for reducing the processing time required to decode telegram. Since a telegram is stored in a tag after information bits are scrambled by an encoder, decoding procedure includes descrambling of received telegram to recover the original information bits. By analyzing the structure of the descrambling shift register circuit, we proposed a parallel descrambling scheme for fast decoding of telegram. By comparing the required number of clocks, it is shown that the proposed scheme significantly outperforms the original one.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.42 no.8 s.338
• /
• pp.11-16
• /
• 2005

This paper proposes a bit manipulation accelerator (BMA) having application specific instructions, which efficiently supports scrambling, convolutional encoding, puncturing, and interleaving. Conventional DSPs cannot effectively perform bit manipulation functions since かey have multiply accumulate (MAC) oriented data paths and word-based functions. However, the proposed accelerator can efficiently process bit manipulation functions using parallel shift and Exclusive-OR (XOR) operations and bit jnsertion/extraction operations on multiple data. The proposed BMA has been modeled by VHDL and synthesized using the SEC $0.18\mu m$ standard cell library and the gate count of the BMA is only about 1,700 gates. Performance comparisons show that the number of clock cycles can be reduced about $40\%\sim80\%$ for scrambling, convolutional encoding and interleaving compared with existing DSPs.

• The Transactions of the Korea Information Processing Society
• /
• v.3 no.3
• /
• pp.478-492
• /
• 1996

For parallel implementations of functional programs without concurrent primitives, the λ-calculus encodings have been introduced. A functional program may be trans for med into a process network using process calculiby the λ-calculus encoding and there sult of a program can be obtained by a deal of communication actions in it's process network. But the λ-calculus encodings cause too many communication actions even in constant expressions. This paper shows the encoding for a combinator program without concurrency primitives which can combine the graph reduction and the process-net reduction using computable processes,'chores'. A 'chore' may have graph reduction functions for primitive operations of constants for which local graph reduction may be possible, and be encoded from a 'G-reducible' subexpression which is obtained by an annotation and trans for mati-on for a combinator program, assuring that it does not include any combinator application. Also, we show that a process network with chores raises less commu-nication actions than one without chores.

• Journal of Magnetics
• /
• v.18 no.4
• /
• pp.422-427
• /
• 2013

The aim of this study was to investigate effects of the number of acquisitions (NEX) on signal-to-noise (SNR) and artifacts in SENSE parallel imaging of magnetic resonance imaging (MRI). 3.0T MR System, 8 Channel sensitivity encoding (SENSE) head coils were used along with an in-vivo phantom. Reference sequence of 3D fast field echo (FFE) was consisted of NEX values of 2, 4, 6, 8, 10 and 12. The T2 turbo spin echo (TSE) sequence used for exams achieved SENSE factors of 1.2, 1.5, 1.8, 2.0, 2.2, 2.5, 2.8, 3.0, 3.2, 3.5, 3.8 and 4.0. Exams were conducted five times for each SENSE factor to measure signal intensity of the object, the posterior phase-encode direction and frequency direction. And SNR was calculated using mean values. SENSE artifacts were identified as background signal intensity in the phase-encoded direction using MRIcro. It was found that SNR increased but SENSE artifacts reduced with NEX of 4, 8 and 12 when the NEX increased in reference scan. It is therefore concluded that image quality can be improved with NEX of 4, 8 and 12 for reference scanning.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.34C no.2
• /
• pp.29-37
• /
• 1997

A new algorithm and parallel architecture for high-speed complex number multiplication is presented, and a prototype chip based on the proposed approach is designed. By employing redundant binary (RB) arithmetic, an N-bit complex number multiplication is simplified to two RB multiplications (i.e., an addition of N RB partial products), which are responsible for real and imaginary parts, respectively. Also, and efficient RB encoding scheme proposed in this paper enables to generate RB partial products without additional hardware and delay overheads compared with binary partial product generation. The proposed approach leads to a highly parallel architecture with regularity and modularity. As a results, it results in much simpler realization and higher performance than the classical method based on real multipliers and adders. As a test vehicle, a prototype 8-b complex number multiplier core has been fabricated using $0.8\mu\textrm{m}$ CMOS technology. It contains 11,500 transistors on the area of about $1.05 \times 1.34 textrm{mm}^2$. The functional and speed test results show that it can safely operate with 200 MHz clock at $V_{DD}=2.5 V$, and consumes about 90mW.

• Computers and Concrete
• /
• v.11 no.6
• /
• pp.541-569
• /
• 2013

There is a wide variety of existing Genetic Algorithms (GA) operators and parameters in the literature. However, there is no unique technique that shows the best performance for different classes of optimization problems. Hence, the evaluation of these operators and parameters, which influence the effectiveness of the search process, must be carried out on a problem basis. This paper presents a comparison for the influence of GA operators and parameters on the performance of the damage identification problem using the finite element model updating method (FEMU). The damage is defined as reduction in bending rigidity of the finite elements of a reinforced concrete beam. A certain damage scenario is adopted and identified using different GA operators by minimizing the differences between experimental and analytical modal parameters. In this study, different selection, crossover and mutation operators are compared with each other based on the reliability, accuracy and efficiency criteria. The exploration and exploitation capabilities of different operators are evaluated. Also a comparison is carried out for the parallel and sequential GAs with different population sizes and the effect of the multiple use of some crossover operators is investigated. The results show that the roulettewheel selection technique together with real valued encoding gives the best results. It is also apparent that the Non-uniform Mutation as well as Parent Centric Normal Crossover can be confidently used in the damage identification problem. Nevertheless the parallel GAs increases both computation speed and the efficiency of the method.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.10 s.352
• /
• pp.45-53
• /
• 2006

In this paper, we proposed a parallel hardware architecture for deblocking filter in K264/AVC. The deblocking filter has high efficiency in H.264/AVC, but it also has high computational complexity. For real time video processing, we chose a two 1-D parallel filter architecture, and tried to reduce memory access using dual-port SRAM. The proposed architecture has been described in Verilog-HDL and synthesized on Hynix 0.25um CMOS Cell Library using Synopsys Design Compiler. The hardware size was about 27.3K logic gates (without On-chip Memory) and the maximum operating frequency was 100Mhz. It consumes 258 clocks to process one macroblock, witch means it can process 47.8 HD1080P(1920pixel* 1080pixel) frames per second. It seems that it can be used for real time H.264/AVC encoding and decoding of various multimedia applications.