• Journal of the Microelectronics and Packaging Society
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• v.18 no.2
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• pp.43-48
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• 2011

The maximum current density of copper electrorefining is 350 A/$m^2$ and the higher current density is required to promote the copper productivity. The 1000 A/$m^2$ high current density is possible when rotating disc electrode is employed to reduce diffusion thickness. The copper electroplating with 1000 A/$m^2$ is possible at 400 rpm. Thiourea and glue were used to improve the electrodeposition behaviors during copper electrorefining process. Potentiodynamic polarization tests were conducted to investigate the effects of additives on copper electrodeposition. Galvanostatic tests were also conducted at 1000 A/$m^2$. Copper were electroplated on cylindrical rotating electrodes to give the uniform flow on the electrode surface. The lowest surface roughness was obtained when 16 ppm thiourea was added to the electrolytes. The surface roughness was increased with glue concentration. The surface hardness was not influenced by addition of glue. The copper nuclei were getting smaller with thiourea concentration, however there is no glue effects on copper nucleation.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.1 s.38
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• pp.1-5
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• 2006

We prepared 80 nm-thick TiSix on each 70 nm-thick amorphous silicon and polysilicon substrate using an RF sputtering with $TiSi_2$ target. TiSix composite silicide layers were stabilized by rapid thermal annealing(RTA) of $800^{\circ}C$ for 20 seconds. Line width of $0.5{\mu}m$ patterns were embodied by photolithography and dry etching process, then each additional annealing process at $750^{\circ}C\;and\;850^{\circ}C$ for 3 hours was executed. We investigated the change of sheet resistance with a four-point probe, and cross sectional microstructure with a field emission scanning electron microscope(FE-SEM) and transmission electron microscope(TEM), respectively. We observe an abrupt change of resistivity and voids at the silicide surface due to interdiffusion of silicide and composite titanium silicide in the amorphous substrates with additional $850^{\circ}C$ annealing. Our result implies that the electrical resistance of composite titanium silicide may be tunned by employing appropriate substrates and annealing condition.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.1
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• pp.75-81
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• 2017

The effects of KOH pretreatment and annealing conditions on the interfacial adhesion and the reliability between epoxy resin and polyimide substrate in the flexible printed circuit board were quantitatively evaluated using $180^{\circ}$ peel test. The initial peel strength of the polyimide without the KOH treatment was 29.4 g/mm and decreased to 10.5 g/mm after 100hrs at $85^{\circ}C/85%$ R.H. temperature/humidity treatment. In case of the polyimide with annealing after KOH treatment, initial peel strength was 29.6 g/mm and then maintained around 27.5 g/mm after $85^{\circ}C/85%$ R.H. temperature/humidity treatment. Systematic X-ray photoelectron spectroscopy analysis results showed that the peel strength after optimum annealing after KOH treatment was maintained high not only due to effective recovery of the polyimide damage by the polyimide surface treatment process, but also effective removal of metallic ions and impurities during various wet process.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.3
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• pp.49-53
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• 2018

Since various methods to form well-aligned nano-/micro- patterns are underlying technologies to fabricate next generation wearable electronic devices, many efforts have been made to realize finer patterns in recent years. Among lots of patterning methods, the present invention includes a nano-transfer printing (n-TP) process which is advantageous in that a processing cost is low and high-resolution patterns can be formed within a short processing time. We successfully achieved pattern formation of highly ordered Pt lines with line-width of 250 nm, 500 nm, and $1{\mu}m$ on transparent and flexible substrates. In addition, we analyzed the durability of the patterns, showing excellent stability of line-shape even after a physical and repeated bending test of 500 times using a bending machine. As a result, it is expected that a n-TP process is very useful for forming various metal patterns, and it is also expected to be applied to wiring and interconnection technology of next generation flexible electronic devices.

• Journal of the Microelectronics and Packaging Society
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• v.10 no.2
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• pp.49-54
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• 2003

We have investigated the effects of hydrogen annealing on the physical and electrical properties of $SrBi_{2}Ta_{2}O_9(SBT)$ thin films in the Pt/SBT/Si (MFS) structure and Pt/SBT/Pt (MFM) one, respectively. The microstructure and electrical characteristics of the SBT films were deteriorated after hydrogen annealing due to the damage of the SBT films during the annealing process. To investigate the reason of the degradation of the SBT films in this work, in particular, the effect of the Pt top electrodes, SBT thin films deposited on Si, Pt, respectively, were annealed with the same process conditions. From the XRD, XPS, P-V, and C-V data, it was seen that the SBT itself was degraded after $H_2$ annealing even without the Pt top electrodes. In addition, the degradation of the SBT films after $H_2$ annealing was accelerated by the catalytic reaction of the Pt top electrodes which is so-called hydrogen degradation. To prevent this phenomenon, we proposed the alternative top electrode material, i.e. Ir, and the electrical properties of the SBT thin films were examined in the $Ir/IrO_2/SBT/IrO_2$ structures before and after the H$_2$ annealing and recovery heat-treatment processes. From the results of the P-V measurement, it could be concluded that Ir is one of the promising candidate as the electrode material for degradation resistance in the MFM structure using SBT thin films.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.1
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• pp.29-33
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• 2011

The current density in copper electroplating is directly related with the productivity and then to increase the productivity, the increase in current density is required. To obtain the high mass flow rate, rotating disk electrode(RDE) was employed. High rotational speed in RDE can increase the mass flow rate and then high speed electroplating was possible using RDE to control mass flow. Two types of cathode were used. One is RDE and another is rotating cylindrical electrode(RCE). A constant-current, constant-voltage and linear sweep voltammetry were applied to investigate current and voltage relationship. The maximum current density without evolution of hydrogen gas was increased with rotational speed. Over 400 rpm, maximum current density was higher than 1000 A/$m^2$. The diffusion coefficients of copper calculated from the slope of the plots are $5.5{\times}10^6\;cm^2\;s^{-1}$ at $25^{\circ}C$ and $10.5{\times}10^6\;cm^2\;s^{-1}$ at $62^{\circ}C$. The stable voltage without evolution of hydrogen gas was -0.05 V(vs Ag/AgCl). Additives were added to prevent dendritic growth on cathode deposits. The surface roughness was analyzed with UV-Vis Spectrophotometer. The reflectance of the copper surface over 600 nm was measured and was related with the surface roughness. As the surface roughness improved, the reflectance was also increased.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.2 s.35
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• pp.105-109
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• 2005

A compact antenna switch module for GSM/DCS dual band applications based on multilayer low temperature co-fired ceramic (LTCC) substrate is presented. Its size is $4.5{\times}3.2{\times}0.8 mm^3$ and insertion loss is lower than 1.0 dB at Rx mode and 1.2 dB at Tx mode. To verify the stability of the developed module to the process window, each block that is diplexer, LPF's and bias circuit is measured by probing method in the variation with the thickness of ceramic layer and the correlation between each block is quantified by calculating the VSWR In the mean while, two types of bias circuits -lumped and distributed - are compared. The measurement of each block and the calculation of VSWR give good information on the behavior of full module. The reaction of diplexer to the thickness is similar to those of LPF's and bias circuit, which means good relative matching and low value of VSWR, so total insertion loss is maintained in quite wide range of the thickness of ceramic layer at both band. And lumped type bias circuit has smaller insertion itself and better correspondence with other circuit than distributed stripline structure. Evaluated ceramic module adopting lumped type bias circuit has low insertion loss and wider stability region of thickness over than 6um and this can be suitable for the mass production. Stability characterization by probing method can be applied widely to the development of ceramic modules with embedded passives in them.

• Journal of the Microelectronics and Packaging Society
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• v.26 no.4
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• pp.101-105
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• 2019

The adhesion reliability of the epoxy molding compound (EMC) and the printed circuit board (PCB) interface is critical to the quality and lifetime of the chip package since the EMC protects PCB from the external environment during the manufacturing, storage, and shipping processes. It is necessary to measure adhesion energy accurately to ensure product reliability by optimizing the manufacturing process during the development phase. This research deals with the measurement of EMC/PCB interfacial adhesion energy of chip package that has warpage induced by the coefficient of thermal expansion (CTE) mismatch. The double cantilever beam (DCB) test was conducted to measure adhesion energy, and the spring back force of specimens with warpage was compensated to calculate adhesion energy since the DCB test requires flat substrates. The result was verified by comparing the adhesion energy of flat chip packages come from the same manufacturing process.

• Journal of the Microelectronics and Packaging Society
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• v.9 no.4
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• pp.1-9
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• 2002

The metallurgical reaction properties between the pad consisted of 0.5 $\mu\textrm{m}$Au/5 $\mu\textrm{m}$Ni/Cu layers on a conventional ball grid array (BGA) substrate and In-15 (wt.%)Pb-5Ag solder ball were characterized during the reflow process and solid aging. During the reflow process of 1 to 5 minutes, it was observed that thin $AuIn_2$ or Ni-In intermetallic layer was formed at the interface of solder/pad. The dissolution rate of the Au layer into the molten solder was about $2\times 10^{-3}$ $\mu\textrm{m}$/sec which is remarkably low in comparison with a eutectic Sn-37Pb solder. After solid aging treatment for 500 hrs at $130^{\circ}C$, the thickness of $Ni_{28}In_{72}$ intermetallic layer was increased to about 3 $\mu\textrm{m}$ in all the conditions nevertheless the initial reflow time was different. These result show that In atoms in the solder alloy were diffused through the $AuIn_2$ phase to react with underlaying Ni layer during solid aging treatment. From the microstructural observation and shear tests, the reaction properties between In-15Pb-5Ag alloy and Au/Ni surface finish were analyzed not to trigger Au-embrittlement in the solder joints unlike Sn-37Pb composition.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.2
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• pp.7-15
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• 2012

Semiconductor packages are increasingly moving toward miniaturization, lighter and multi-functions for mobile application, which requires highly integrated multi-stack package. To meet the industrial demand, the package and silicon chip become thinner, and ultra-thin packages will show serious reliability problems such as warpage, crack and other failures. These problems are mainly caused by the mismatch of various package materials and geometric dimensions. In this study we perform the numerical analysis of the warpage deformation and thermal stress of 4-layer stacked FBGA package after EMC molding and reflow process, respectively. After EMC molding and reflow process, the package exhibits the different warpage characteristics due to the temperature-dependent material properties. Key material properties which affect the warpage of package are investigated such as the elastic moduli and CTEs of EMC and PCB. It is found that CTE of EMC material is the dominant factor which controls the warpage. The results of RSM optimization of the material properties demonstrate that warpage can be reduced by $28{\mu}m$. As the silicon die becomes thinner, the maximum stress of each die is increased. In particular, the stress of the top die is substantially increased at the outer edge of the die. This stress concentration will lead to the failure of the package. Therefore, proper selection of package material and structural design are essential for the ultra-thin die packages.