• Proceedings of the KIEE Conference
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• 1996.07a
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• pp.540-542
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• 1996

A detailed model of a photo voltaic array written in PSPlCE is presented in this paper. It is likely that solar cell arrays in photovoltaic system is shadowed partly by clouds, buildings. By the effects of partial shadowing, not only the output power of solar cell arrays is decreased, but also shadowed cells are reversely biased and damaged in some cases. In this paper, by analyzing the output characteristics of solar cell arrays according to various shadow patterns, we investigate solar cell arrays connection of prevention the shadowing effects to the utmost.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.21 no.5
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• pp.106-111
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• 2007

After the semiconductor processing, wafer is attracted by ESC(Electrostatic Chuck) with remaining electric charge. That causes too many problems for examples, sliding of wafer, popping or broken. This paper presents the model of ESC for silicon wafer, which is modeled by electrical circuit component such as capacitor. The simulations using PSpice result in the phenomenon of silicon wafer was charged by ESC. In this paper we suggest the discharging method. for wafer.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.17 no.6
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• pp.83-88
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• 2003

This paper analyses a fault operation due to the effect of miller capacitance, which severely influences the performance of the IPMs based on computer-aided simulations, and also it presents a good solution to solve that problem. A miller capacitance existed between gate and collect is very closely related to the stray capacitance formed between gate and emitter, and the value of gate resistor. These relationships are proved by the computer-aided simulation. Based on the PSpice simulation results, a customized IPM employing an auxiliary circuit is presented to minimize a fault operation. And it is compared to the standard IPM by the experimental waveform. As a result, it is verified that a customized IPM has a voltage margin to prevent a fault operation approx. 3 [V].

• Journal of Electrical Engineering and Technology
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• v.3 no.1
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• pp.36-42
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• 2008

In a gas insulated substation (GIS), Very Fast Transient Over-voltages (VFTOs) are generated due to switching operations and ground faults. These fast transients are associated with high frequency components of the order of a few hundreds of MHz. These transients may cause internal faults i.e., layer-to-layer faults or minor faults in a capacitively graded bushing, which is one of the important pieces of terminal equipment for GIS. In the present study, the PSPICE model has been developed to calculate the voltage distribution across the layers of 420kV graded bushing for high frequency pulses of rise time 1 to 50ns, which simulate the VFTO. For this simulation, an equivalent electrical network of bushing with different equivalent layers has been considered. The effect of different equivalent layers modeling circuits on the non-uniform voltage factor has been analysed. The influence of copper strip inductance on voltage distribution across layers has also been analysed for various rise times of high frequency transients. Finally, the leakage current of the bushing is calculated for evaluating the bushing condition under these transients.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.18 no.2
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• pp.68-74
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• 2004

This paper presents a novel hybrid multilevel inverter using DC-Link voltage combination in order to improve the waveshape of output voltage and reduce harmonics. The proposed multilevel inverter can generate an 11-level output voltage. It employs three H-bridge cell, which consists of single phase full-bridge inverter module. Among them, two modules are used for level generation, and one module performs PWM switching. Nine levels are synthesised by the level inverter, and two levels are added to output by the PWM inverter. As a result, it generates an 11-level. The operational principles are explained in depth, and the validity of the proposed system is verified through the PSpice simulation and experimental results based on a prototype.

• Journal of the Korea Society of Computer and Information
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• v.3 no.2
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• pp.77-84
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• 1998

The continuous time signal system by development of CMOS technology have been receiving consideration attention. In this paper, Low pass filter using CMOS floating resistor have been designed with cut off frequency for speech signal processing. Especially a new floating resistor consisting entirely of CMOS devices in saturation has been developed. Linearity within $\pm$0.04% is achieved through nonlineartiy via current mirrors over an applied range of $\pm$1V. The frequency response exceeds 10MHz, and the resistors are expected to be useful in implementing integrated circuit active RC filters. The low pass filter designed using this method has simpler structure than switched capacitor filter. So reduce the chip area. The characteristics of the designed low pass filter using this method are simulated by pspice program.

• The Transactions of the Korean Institute of Power Electronics
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• v.14 no.6
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• pp.488-495
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• 2009

This paper proposes a new AC/DC RPPB(Resonant Piezo-Powered Boost) converter for energy harvesting using a piezoelectric device which converts mechanical vibration energy to electrical energy. The AC/DC RPPB converter can operate with only the harvested energy without an additional power conversion circuit for switching circuit and transfer energy to a load of which the voltage is higher than piezoelectric voltage. With the review of published topologies of the converter for energy harvesting, the operation principle of the AC/DC RPPB converter, and the results of PSPICE simulation and experiment are presented to prove the feasibility of the new converter for the energy harvesting.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.10
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• pp.2123-2135
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• 1997

In this paepr, we consider resistive shorts on drain-source, drain-gate, and gate-source as well as opens in MOSFETs included in typical memory cell of VLSI SRAM. Behavior of memeory is observed by analyzing voltage at storage nodes of memeory and IDDQ(quiescent power supply current) through PSPICE simulation. Using this behavioral analysis, an effective testing algorithm of complexity O(N) which can be applied to both functional testing and IDDQ testing simultaeously is proposed. Built-In Self Test(BIST) circuit which detects faults in memories and Built-In Current Sensor(BICS) which monitors the power supply bus for abnormalities in quescent current are developed and imprlemented to improve the quality and efficiency of testing. Implemented BIST and BICS circuits can detect locations of faults and defects in order to repair faulty memories.

• The Journal of the Korea institute of electronic communication sciences
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• v.5 no.1
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• pp.17-22
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• 2010

Generally, there are Chua's Circuit, Lorenz Circuit and Duffing circuit in the chaos circuit. Among these chaos circuits, Chua's circuit is well known to make the electronic parts easily. Chua's circuit is the constitute of the linearelements. These are constitute of Resistor component(R), inductor component(L), capacitor(C), and nonlinear element which is constitute of nonlinear resistor. However, L element have a difficult problem to implement real hardware by using commercial parts. Due to this, it has a saturation characteristic. In this paper, we analyzed the simplified Chua's circuit which is replace L to C by PSPICE program. Because L element has a difficult problem to make a real hardware, L has a saturation characteristic and we also confirm this analysis as the result.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.10 no.5
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• pp.52-56
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• 1996

Fluorescent lamps are widely accepted to energy efficient commercial lighting applications. In designing a fluorescent lamp system, a ballast design heavily relies on the characteristic of a fluorescent lamp under consideration. Especially, at startup time, the transient characteristic of a fluorescent lamp puts much tighter specification of a design. In this paper, based on the transient characteristic at the startup time, a transient behavioral model of a fluorescent lamp is presented with an equivalent circuit. The model is applicable to the wide range of fluorescent lamps provided by different manufacturers. The experimental results are compared with the results provided by PSPICE simulation. The result shows the model is effective In practice. As a result, we could identify more accurate startup constraints to decide the design of either an electro mechanical or an electronic ballast.