• Journal of Biosystems Engineering
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• v.29 no.6 s.107
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• pp.521-530
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• 2004

The solar powered water pump is very ideal equipment because solar power is more intensive when the water is more needed in summer and it is very helpful in the rural area, in which electrical power is not available. The average solar radiation power is $3.488\;kWh/(m^2{\cdot}day)$ in Korea. In this study, the experimental system of the water pump driven by the radiation energy were designed, assembled, tested and analyzed fur realizing the solar powered water pump. Energy conversion ken radiation energy to mechanical energy by using n-pentane as operating material was done and the water pumping cycles were able to be continued. The quantity of the water pumped per cycle ranged from 2 L to 10 L depending on the level of the valve open area far the vapour supply. The average quantity was about 4,366 cc. The thermal efficiency was about $0.018\%$. The pressure level of the n-pentane vapour in flash tank was about $110\~150\;kPa$ and that in the water tank was $93\~130\;kPa$. The pressure in the condenser during cycles was maintained as about 70 kPa. The condensation of the n-pentane vapour in the water tank was increased with the cycles even though the internal and external insulation were done. Air tank performance was better with increasing of the water piston displacement and the water could be pumped with the water piston displacement becoming higher than 6,500 cc.

• Journal of the Computational Structural Engineering Institute of Korea
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• v.32 no.2
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• pp.87-92
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• 2019

In this paper, we have verified a low-voltage EM(elasto-magnetic) sensing technique for tensile force management of PSC(prestressed concrete) internal tendon in order to apply the technique to actual construction sites where stable power supply is difficult. From observation of past domestic and overseas PSC structural accident cases, it was found that PS tension is very important to maintain structural stability. In this paper, we have tried to measure the tensile force from a magnetic hysteresis curve through EM sensors according to voltage value by using relation between magnetostriction and stress of ferromagnetic material based on elastic-magnetic theory. For this purpose, EM sensor of double cylindrical coil type was fabricated and tensile force test equipment for PS tendon using hydraulic tensioning device was constructed. The experiment was conducted to confirm relationship between changes of permeability and tensile force from the measurement results of the maximum / minimum voltage amount. The change of magnetic hysteresis curve with magnitude of tensile force was also measured by reducing amount of voltage step by step. As a result, the slope of estimation equation in accordance with magnitude of magnetic field decreases with the voltage reduction. But it was confirmed a similar pattern of change of magnetic permeability for the magnetic hysteresis loop. So, in this study, it is considered that it is possible to manage the tensions of PSC internal tendon using EM sensing technique in low-voltage state.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.21-27
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• 2008

This paper describes a CMOS 16:1 binary-tree multiplexer(MUX) using $0.18-{\mu}m$ technology. To provide immunity for wide frequency range and process-and-temperature variations, the MUX adopts several delay compensation techniques. Simulation results show that the proposed MUX maintains the setup margins and hold margins close to the optimal value, i.e., 0.5UI, in wide frequency-range and in wide process-and-temperature variations, with standard deviation of 0.05UI approximately. These results represent that these proposed delay compensations are effective and the reliability is much improved although CMOS logic circuits are sensitive to those variations. The MUX is fabricated using $0.18-{\mu}m$ CMOS process, and tested with a test board. At power supply voltage of 1.8-V, maximum data-rate and area of the MUX is 1.65-Gb/s and 0.858 $mm^2$, respectively. The MUX dissipates a power of 24.12 mW, and output eye opening is 272.53 mV, 266.55 ps at 1.65-Gb/s operation.

• Journal of information and communication convergence engineering
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• v.10 no.2
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• pp.187-193
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• 2012

A 1 GHz CMOS fast-lock phase-locked loop (PLL) is proposed to support the quick wake-up time of mobile consumer electronic devices. The proposed fast-lock PLL consists of a conventional charge-pump PLL, a frequency-to-digital converter (FDC) to measure the frequency of the input reference clock, and a digital-to-analog converter (DAC) to generate the initial control voltage of a voltage-controlled oscillator (VCO). The initial control voltage of the VCO is driven toward a reference voltage that is determined by the frequency of the input reference clock in the initial mode. For the speedy measurement of the frequency of the reference clock, an FDC with a parallel architecture is proposed, and its architecture is similar to that of a flash analog-to-digital converter. In addition, the frequency-to-voltage converter used in the FDC is designed simply by utilizing current integrators. The circuits for the proposed fast-lock scheme are disabled in the normal operation mode except in the initial mode to reduce the power consumption. The proposed PLL was fabricated by using a 0.18-${\mu}m$ 1-poly 6-metal complementary metal-oxide semiconductor (CMOS) process with a 1.8 V supply. This PLL multiplies the frequency of the reference clock by 10 and generates the four-phase clock. The simulation results show a reduction of up to 40% in the worstcase PLL lock time over the device operating conditions. The root-mean-square (rms) jitter of the proposed PLL was measured as 2.94 ps at 1 GHz. The area and power consumption of the implemented PLL are $400{\times}450{\mu}m^2$ and 6 mW, respectively.

• The Journal of the Korea Contents Association
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• v.10 no.2
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• pp.72-80
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• 2010

The 1Gbps clock and data recovery (CDR) circuit using the proposed multi-point phase detector (PD) is presented. The proposed phase detector generates up/down signals comparing 3-point that is data transition point and clock rising/falling edge. The conventional PD uses the pulse width modulation (PWM) that controls the voltage controlled oscillator (VCO) using the width of a pulse period's multiple. However, the proposed PD uses the pulse number modulation (PNM) that regulates the VCO with the number of half clock cycle pulse. Therefore the proposed PD can controls VCO preciously and reduces the jitter. The CDR circuit is tested using 1Gbps $2^{31}-1$ pseudo random bit sequence (PRBS) input data. The designed CDR circuit shows that is capable of recovering clock and data at rates of 1Gbps. The recovered clock jitter is 7.36ps at 1GHz and the total power consumption is about 12mW. The proposed circuit is implemented using a 0.18um CMOS process under 1.8V supply.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.2
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• pp.309-316
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• 2019

In this paper, a low-jitter delay-locked loop that compensates for local clock skew is presented. The proposed DLL consists of a phase splitter, a phase detector(PD), a charge pump, a bias generator, a voltage-controlled delay line(VCDL), and a level converter. The VCDL uses self-biased delay cells using current mode logic(CML) to have insensitive characteristics to temperature and supply noises. The phase splitter generates two reference clocks which are used as the differential inputs of the VCDL. The PD uses the only single clock from the phase splitter because the PD in the proposed circuit uses CMOS logic that consumes less power compared to CML. Therefore, the output of the VCDL is also converted to the rail-to-rail signal by the level converter for the PD as well as the local clock distribution circuit. The proposed circuit has been designed with a $0.13-{\mu}m$ CMOS process. A global CLK with a frequency of 1-GHz is externally applied to the circuit. As a result, after about 19 cycles, the proposed DLL is locked at a point that the control voltage is 597.83mV with the jitter of 1.05ps.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.118-124
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• 2008

For forward error correction, DVB-S2, which is the digital video broadcasting forward error coding and modulation standard for satellite television, uses a system based the concatenation of BCH with LDPC inner coding. In DVB-S2 the LDPC codes are defined for 11 different code rates, which means that a DVB-S2 LDPC decoder should support multiple code rates. Seven of the 11 code rates, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, and 9/10, are regular and the rest four code rates, 1/4, 1/3, 2/5, and 1/2, are irregular. In this paper we propose a flexible decoder for the regular LDPC codes. We combined the partially parallel decoding architecture that has the advantages in the chip size, the memory efficiency, and the processing rate with Benes network to implement a DVB-S2 LDPC decoder that can support multiple code rates with a block size of 64,800 and can configure the interconnection between the variable nodes and the check nodes according to the parity-check matrix. The proposed decoder runs correctly at the frequency of 200MHz enabling 193.2Mbps decoding throughput. The area of the proposed decoder is $16.261m^2$ and the power dissipation is 198mW at a power supply voltage of 1.5V.

• Journal of Animal Environmental Science
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• v.10 no.3
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• pp.141-154
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• 2004

The solar powered water pump is very ideal equipment because solar power is more intensive when the water is more needed in summer and it is very helpful in the rural area, in which the electrical power is not available. The average so]ar radiation energy is 3.488 kWh/($m^2{\cdot}day$) in Korea. In this study, the automatic control logic and system of the water pump driven by the radiation energy were studied, designed, assembled, tested and analyzed for realizing the solar powered water pump. The experimental system was operated automatically and the cycle was continued. The average quantity of the water pumped per cycle was about 5,320 cc. The cycle time was about 4.9 minutes. The thermal efficiency of the system was about $0.030\%$. The pressure level of the n-pentane vapour in flash tank was 150$\%$450 hPa(gauge) which was set by the computer program for the control of the vapour supply. The pressure in the condenser and air tank during cycles was maintained as about 600 hPa and 1,200 hPa respectively. The water could be pumped by the amount of 128kg/($m^2{\cdot}day$) with the efficiency of $0.1\%$ and the pumping head of 10 m for the average solar energy in Korea.