• Title/Summary/Keyword: PPS (P-type MOSFET pass structure)

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Improvement of Electrostatic Discharge (ESD) Protection Performance through Structure Modification of N-Type Silicon Controlled Rectifier Device (N형 실리콘 제어 정류기 소자의 구조 변형을 통한 정전기 보호성능의 향상에 대한 연구)

  • Yang, Jun-Won;Seo, Yong-Jin
    • Journal of Satellite, Information and Communications
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    • v.8 no.4
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    • pp.124-129
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    • 2013
  • An electrostatic discharge (ESD) protection device, so called, N-type SCR with P-type MOSFET pass structure (NSCR_PPS), was analyzed for high voltage I/O applications. A conventional NSCR_PPS device shows typical SCR-like characteristics with extremely low snapback holding voltage, which may cause latch-up problem during normal operation. However, a modified NSCR_PPS device with counter pocket source(CPS) and partial p-type well(PPW) structure demonstrates highly latch-up immune current-voltage characteristics.

Effects on the ESD Protection Performance of PPS(PMOS Pass Structure) Embedded N-type Silicon Controlled Rectifier Device with different Partial P-Well Structure (PPS 소자가 삽입된 N형 SCR 소자에서 부분웰 구조가 정전기 보호 성능에 미치는 영향)

  • Yang, Jun-Won;Seo, Yong-Jin
    • Journal of Satellite, Information and Communications
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    • v.9 no.4
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    • pp.63-68
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    • 2014
  • Electrostatic Discharge(ESD) protection performance of PPS(PMOS pass structure) embedded N-type silicon controlled rectifier(NSCR_PPS) device with different partial p-well(PPW) structure was discussed for high voltage I/O applications. A conventional NSCR_PPS standard device shows typical SCR-like characteristics with low on-resistance, low snapback holding voltage and low thermal breakdown voltage, which may cause latch-up problem during normal operation. However, our proposed NSCR_PPS devices with modified PPW demonstrate the stable ESD protection performance with high latch-up immunity.

Study on the Optimal CPS Implant for Improved ESD Protection Performance of PMOS Pass Structure Embedded N-type SCR Device with Partial P-Well Structure (PMOS 소자가 삽입된 부분웰 구조의 N형 SCR 소자에서 정전기 보호 성능 향상을 위한 최적의 CPS 이온주입에 대한 연구)

  • Yang, Jun-Won;Seo, Yong-Jin
    • Journal of Satellite, Information and Communications
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    • v.10 no.4
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    • pp.1-5
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    • 2015
  • The ESD(electrostatic discharge) protection performance of PPS(PMOS pass structure) embedded N-type silicon controlled rectifier(NSCR_PPS) device with different partial p-well(PPW) structure was discussed for high voltage I/O applications. A conventional NSCR_PPS standard device shows typical SCR-like characteristics with low on-resistance, low snapback holding voltage and low thermal breakdown voltage, which may cause latch-up problem during normal operation. However, our proposed NSCR_PPS devices with modified PPW_PGM(primary gate middle) and optimal CPS(counter pocket source) implant demonstrate the stable ESD protection performance with high latch-up immunity.

Latchup Characteristics of N-Type SCR Device for ESD Protection (정전기 보호를 위한 n형 SCR 소자의 래치업 특성)

  • Seo, Y.J.;Kim, K.H.;Lee, W.S.
    • Proceedings of the KIEE Conference
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    • 2006.07c
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    • pp.1372-1373
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    • 2006
  • An electrostatic discharge (ESD) protection device, so called, N-type SCR with P-type MOSFET pass structure (NSCR_PPS), was analyzed for high voltage I/O applications. A conventional NSCR_PPS device shows typical SCR-like characteristics with extremely low snapback holding voltage, which may cause latchup problem during normal operation. However, a modified NSCR_PPS device with proper junction/channel engineering demonstrates highly latchup immune current- voltage characteristics.

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Optimal Design of ESD Protection Device with different Channel Blocking Ion Implantation in the NSCR_PPS Device (NSCR_PPS 소자에서 채널차단 이온주입 변화에 따른 최적의 정전기보호소자 설계)

  • Seo, Yong-Jin;Yang, Jun-Won
    • Journal of Satellite, Information and Communications
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    • v.11 no.4
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    • pp.21-26
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    • 2016
  • The ESD(electrostatic discharge) protection performance of PPS(PMOS pass structure) embedded N-type silicon controlled rectifier(NSCR_PPS) device with different implant of channel blocking region was discussed for high voltage I/O applications. A conventional NSCR standard device shows low on-resistance, low snapback holding voltage and low thermal breakdown voltage, which may cause latch-up problem during normal operation. However, our proposed NSCR_PPS devices with modified channel blocking structure demonstrate the improved ESD protection performance as a function of channel implant variation. Therefore, the channel blocking implant was a important parameter. Since the modified device with CPS_PDr+HNF structure satisfied the design window, we confirmed the applicable possibility as a ESD protection device for high voltage operating microchips.

Effects of the ESD Protection Performance on GPNS(Gate to Primary N+ diffusion Space) Variation in the NSCR_PPS Device (NSCR_PPS 소자에서 게이트와 N+ 확산층 간격의 변화가 정전기 보호성능에 미치는 영향)

  • Yang, Jun-Won;Seo, Yong-Jin
    • Journal of Satellite, Information and Communications
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    • v.10 no.4
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    • pp.6-11
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    • 2015
  • The ESD(electrostatic discharge) protection performance of PPS(PMOS pass structure) embedded N-type silicon controlled rectifier(NSCR_PPS) device with different GPNS(Gate to Primary $N^+$ Diffusion Space) structure was discussed for high voltage I/O applications. A conventional NSCR_PPS standard device with FPW(Full P-Well) structure and non-CPS(Counter Pocket Source) implant shows typical SCR-like characteristics with low on-resistance(Ron), low snapback holding voltage(Vh) and low thermal breakdown voltage(Vtb), which may cause latch-up problem during normal operation. However, our proposed NSCR_PPS devices with modified PPW(Partial P-Well) structure and optimal CPS implant demonstrate the improved ESD protection performance as a function of GPNS variation. GPNS was a important parameter, which is satisfied design window of ESD protection device.