• Title/Summary/Keyword: PNP BJT

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The Modeling of the Transistor Saturation Current of the BJT for Integrated Circuits Considering the Base (베이스 영역의 불순물 분포를 고려한 집적회로용 BJT의 역포화전류 모델링)

  • 이은구;김태한;김철성
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.40 no.4
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    • pp.13-20
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    • 2003
  • The model of the transistor saturation current of the BJT for integrated circuits based upon the semiconductor physics is proposed. The method for calculating the doping profile in the base region using process conditions is presented and the method for calculating the base Gummel number of lateral PNP BJT and vertical NPN BJT is proposed. The transistor saturation currents of NPN BJT using 20V and 30V process conditions obtained from the proposed method show an average relative error of 6.7% compared with the measured data and the transistor saturation currents of PNP BJT show an average relative error of 6.0% compared with the measured data.

A study on the method of the calculation of the base Gummel number of the PNP BJT for integrated circuits (집적회로용 PNP BJT의 베이스 Gummel Number 계산 방법에 관한 연구)

  • Lee, Eun-Gu;Lee, Dong-Ryul;Kim, Tae-Han;Kim, Cheol-Seong
    • Proceedings of the KIEE Conference
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    • 2002.11a
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    • pp.141-144
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    • 2002
  • The method of the analysis of the base Gummel number of the PNP BJT(Bipolar Junction Transistor) for integrated circuits based upon the semiconductor physics is proposed and the method of calculating the doping profile of the base region using process conditions is presented. The transistor saturation current obtained from the proposed method of PNP BJT using 20V and 30V process shows an averaged relative error of 6.7% compared with the measured data.

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Turn-off time improvement by fast neutron irradiation on pnp Si Bipolar Junction Transistor

  • Ahn, Sung Ho;Sun, Gwang Min;Baek, Hani
    • Nuclear Engineering and Technology
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    • v.54 no.2
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    • pp.501-506
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    • 2022
  • Long turn-off time limits high frequency operation of Bipolar Junction Transistors (BJTs). Turn-off time decreases with increases in the recombination rate of minority carriers at switching transients. Fast neutron irradiation on a Si BJT incurs lattice damages owing to the displacement of silicon atoms. The lattice damages increase the recombination rate of injected holes with electrons, and decrease the hole lifetime in the base region of pnp Si BJT. Fast neutrons generated from a beryllium target with 30 MeV protons by an MC-50 cyclotron were irradiated onto pnp Si BJTs in experiment. The experimental results show that the turn-off time, including the storage time and fall time, decreases with increases in fast neutron fluence. Additionally, it is confirmed that the base current increases, and the collector current and base-to-collector current amplification ratio decrease due to fast neutron irradiation.

A Study on the SPICE Model Parameter Extraction Method for the BJT DC Model (BJT의 DC 해석 용 SPICE 모델 파라미터 추출 방법에 관한 연구)

  • Lee, Un-Gu
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.58 no.9
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    • pp.1769-1774
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    • 2009
  • An algorithm for extracting the BJT DC model parameter values for SPICE model is proposed. The nonlinear optimization method for analyzing the device I-V data using the Levenberg-Marquardt algorithm is proposed and the method for calculating initial conditions of model parameters to improve the convergence characteristics is proposed. The base current and collector current obtained from the proposed method shows the root mean square error of 6.04% compared with the measured data of the PNP BJT named 2SA1980.

Pyro Squib Circuit Design with Stable Constant Current Driving Method (안정적인 정전류 구동 방식의 파이로 스퀴브 회로 설계)

  • Soh, KyoungJae
    • Journal of the Korea Institute of Military Science and Technology
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    • v.25 no.5
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    • pp.545-551
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    • 2022
  • We proposed a design method for constant current pyro squib circuit. The current method using N MOSFET for the stability problem has a weakness of the current change, requiring a new design. This paper identified the problem with conventional squib circuit where the current is reduced by 25 % when maximum resistance is 3 ohms. Thus, we proposed a stable constant current driving circuit using P MOSFET and PNP BJT. We confirmed stable constant circuit operation through simulations and measurements of the proposed circuit design where the current did not change until the resistance reached 3 ohms.

A Study on a New ESD Protection Circuit with Parasitic PNP BJT Insertion Type with High Robustness Characteristics Based on SCR (SCR 기반 고감내 특성을 갖는 기생 PNP BJT 삽입형 새로운 ESD 보호회로에 관한 연구)

  • Chae, Hee-Guk;Do, Kyoung-Il;Seo, Jeong-Yun;Seo, Jeong-Ju;Koo, Yong-Seo
    • Journal of IKEEE
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    • v.22 no.1
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    • pp.80-86
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    • 2018
  • In this paper, we propose a new PNP bipolar insertion type ESD protection circuit with improved electrical characteristics than the existing ESD protection circuits SCR and LVTSCR. The proposed circuit has 8.59V trigger voltage which is about 9V lower than that of the conventional SCR, and the parasitic PNP has one more operation and high robustness characteristics. For the practical design of the proposed ESD protection circuit, the holding voltage was increased by increasing the base length of the parasitic PNP while increasing the variable L. To verify the electrical characteristics of the proposed device, Synopsys T-CAD simulator was used.

A Study on the Method of the Analysis of the Base Gummel Number of the BJT for Integrated Circuits (직접회로용 BJT의 베이스 Gummel Number 해석 방법에 관한 연구)

  • 이은구;김철성
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.52 no.2
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    • pp.74-79
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    • 2003
  • The method of the analysis of the base Gummel number of the BJT(Bipolar Junction Transistor) for integrated circuits based upon the semiconductor physics is proposed and the method of calculating the doping profile of the base region using process conditions is presented. The transistor saturation current obtained from the proposed method of NPN BJT using 20V and 30V process shows an averaged relative error of 6.7% compared with the measured data and the transistor saturation current of PNP BJT shows an averaged relative error of 9.2% compared with the measured data

Effects of Fast Neutron Irradiation on Switching of Silicon Bipolar Junction Transistor

  • Sung Ho Ahn;Gwang Min Sun
    • Journal of Radiation Protection and Research
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    • v.48 no.3
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    • pp.124-130
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    • 2023
  • Background: When bipolar junction transistors (BJTs) are used as switches, their switching characteristics can be deteriorated because the recombination time of the minority carriers is long during turn-off transient. When BJTs operate as low frequency switches, the power dissipation in the on-state is large. However, when BJTs operate as high frequency switches, the power dissipation during switching transients increases rapidly. Materials and Methods: When silicon (Si) BJTs are irradiated by fast neutrons, defects occur in the Si bulk, shortening the lifetime of the minority carriers. Fast neutron irradiation mainly creates displacement damage in the Si bulk rather than a total ionization dose effect. Defects caused by fast neutron irradiation shorten the lifetime of minority carriers of BJTs. Furthermore, these defects change the switching characteristics of BJTs. Results and Discussion: In this study, experimental results on the switching characteristics of a pnp Si BJT before and after fast neutron irradiation are presented. The results show that the switching characteristics are improved by fast neutron irradiation, but power dissipation in the on-state is large when the fast neutrons are irradiated excessively. Conclusion: The switching characteristics of a pnp Si BJT were improved by fast neutron irradiation.

A Study on ESD Protection Circuit with High Holding Voltage with Parallel PNP and N+ difrt inserted (Parallel PNP 및 N+ drift가 삽입된 높은 홀딩전압특성을 갖는 ESD보호회로에 관한 연구)

  • Kwak, Jae-Chang
    • Journal of IKEEE
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    • v.24 no.3
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    • pp.890-894
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    • 2020
  • In this paper, we propose an ESD protection device with improved electrical characteristics through structural changes of LVTSCR, a typical ESD protection device. The proposed ESD protection device has a higher holding voltage than the existing LVTSCR by inserting a long N+ drift region and additional P-Well and N-Well, and improves the latch-up immunity, a chronic disadvantage of a general SCR-based ESD protection device. In addition, the effective base width of parasitic BJTs was set as a design variable, and the electrical characteristics of the proposed ESD protection device were verified through Synopsys' TCAD simulation so that it can be applied to the required application by applying the N-Stack technology.

A DC-DC Converter Design for OLED Display Module (OLED Display Module용 DC-DC 변환기 설계)

  • Lee, Tae-Yeong;Park, Jeong-Hun;Kim, Jeong-Hoon;Kim, Tae-Hoon;Vu, Cao Tuan;Kim, Jeong-Ho;Ban, Hyeong-Jin;Yang, Gweon;Kim, Hyoung-Gon;Ha, Pan-Bong;Kim, Young-Hee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.12 no.3
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    • pp.517-526
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    • 2008
  • A one-chip DC-DC converter circuit for OLED(Organic Light-Emitting Diode) display module of automotive clusters is newly proposed. OLED panel driving voltage circuit, which is a charge-pump type, has improved characteristics in miniaturization, low cost and EMI(Electro-Magnetic Interference) compared with DC-DC converter of PWM(Pulse Width Modulator) type. By using bulk-potential biasing circuit, charge loss due to parasitic PNP BJT formed in charge pumping, is prevented. In addition, the current dissipation in start-up circuit of band-gap reference voltage generator is reduced by 42% and the layout area of ring oscillator is reduced by using a logic voltage VLP in ring oscillator circuit using VDD supply voltage. The driving current of VDD, OLED driving voltage, is over 40mA, which is required in OLED panels. The test chip is being manufactured using $0.25{\mu}m$ high-voltage process and the layout area is $477{\mu}m{\times}653{\mu}m$.