• Title/Summary/Keyword: PMIC

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Low-area Dual mode DC-DC Buck Converter with IC Protection Circuit (IC 보호회로를 갖는 저면적 Dual mode DC-DC Buck Converter)

  • Lee, Joo-Young
    • Journal of IKEEE
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    • v.18 no.4
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    • pp.586-592
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    • 2014
  • In this paper, high efficiency power management IC(PMIC) with DT-CMOS(Dynamic threshold voltage Complementary MOSFET) switching device is presented. PMIC is controlled PWM control method in order to have high power efficiency at high current level. The DT-CMOS switch with low on-resistance is designed to decrease conduction loss. The control parts in Buck converter, that is, PWM control circuit consist of a saw-tooth generator, a band-gap reference(BGR) circuit, an error amplifier, comparator circuit, compensation circuit, and control block. The saw-tooth generator is made to have 1.2MHz oscillation frequency and full range of output swing from supply voltage(3.3V) to ground. The comparator is designed with two stage OP amplifier. And the error amplifier has 70dB DC gain and $64^{\circ}$ phase margin. DC-DC converter, based on current mode PWM control circuits and low on-resistance switching device, achieved the high efficiency nearly 96% at 100mA output current. And Buck converter is designed along LDO in standby mode which fewer than 1mA for high efficiency. Also, this paper proposes two protection circuit in order to ensure the reliability.

Stability and PSR(Power-Supply Rejection) Models for Design Optimization of Capacitor-less LDO Regulators (회로 최적화를 위한 외부 커패시터가 없는 LDO 레귤레이터의 안정도와 PSR 성능 모델)

  • Joo, Soyeon;Kim, Jintae;Kim, SoYoung
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.26 no.1
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    • pp.71-80
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    • 2015
  • LDO(Low Drop-Out) regulators have become an essential building block in modern PMIC(Power Managment IC) to extend battery life of electronic devices. In this paper, we optimize capacitor-less LDO regulator via Geometric Programming(GP) designed using Dongbu HiTek $0.5{\mu}m$ BCDMOS process. GP-compatible models for stability and PSR of LDO regulators are derived based on monomial formulation of transistor characteristics. Average errors between simulation and the proposed model are 9.3 % and 13.1 %, for phase margin and PSR, respectively. Based on the proposed models, the capacitor-less LDO optimization can be performed by changing the PSR constraint of the design. The GP-compatible performance models developed in this work enables the design automation of capacitor-less LDO regulator for different design target specification.

Design of 2-4 Cell Li-ion Multi Battery Protection Analog Front End(AFE) IC (2-4 cell 리튬이온 멀티 배터리 보호회로 Analog Front End(AFE) IC 설계)

  • Kim, Sun-Jun;Kim, Jun-Sik;Park, Shi-Hong
    • Journal of IKEEE
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    • v.15 no.4
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    • pp.324-329
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    • 2011
  • In recent years, the performance and functions of portable devices has increased. so it requires more power efficiency and energy density while using the battery for a long time. therefore Battery pack which are made up from several battery cells in series in order to achieve higher operating voltage is being used. when using a Li-ion battery, we need a protection circuit to protect from overcharge, over discharge, high temperature and over current. Also, when using battery pack, we need to Cell voltage balancing circuit that each cell in tune with the balancing. In this paper, the proposed IC is applicable by mobile devices as well as E-bike, hybrid vehicles, electric vehicles, and is expected to contribute to the development of domestic PMIC.

Design of Small-Area MTP Memory Based on a BCD Process (BCD 공정 기반 저면적 MTP 설계)

  • Soonwoo Kwon;Li Longhua;Dohoon Kim;Panbong Ha;Younghee Kim
    • Journal of IKEEE
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    • v.28 no.1
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    • pp.78-89
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    • 2024
  • PMIC chips based on a BCD process used in automotive semiconductors require multi-time programmable (MTP) intellectual property (IP) that does not require additional masks to trim analog circuits. In this paper, MTP cell size was reduced by about 18.4% by using MTP cells using PMOS capacitors (PCAPs) instead of NMOS capacitors (NCAPs) in MTP cells, which are single poly EEPROM cells with two transistors and one MOS capacitor for small-area MTP IP design. In addition, from the perspective of MTP IP circuit design, the two-stage voltage shifter circuit is applied to the CG drive circuit and TG drive circuit of MTP IP design, and in order to reduce the area of the DC-DC converter circuit, the VPP (=7.75V), VNN (=-7.75V) and VNNL (=-2.5V) charge pump circuits using the charge pumping method are placed separately for each charge pump.

High Efficiency Buck-Converter with Short Circuit Protection

  • Cho, Han-Hee;Park, Kyeong-Hyeon;Cho, Sang-Woon;Koo, Yong-Seo
    • IEIE Transactions on Smart Processing and Computing
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    • v.3 no.6
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    • pp.425-429
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    • 2014
  • This paper proposes a DC-DC Buck-Converter with DT-CMOS (Dynamic Threshold-voltage MOSFET) Switch. The proposed circuit was evaluated and compared with a CMOS switch by both the circuit and device simulations. The DT-CMOS switch reduced the output ripple and the conduction loss through a low on-resistance. Overall, the proposed circuit showed excellent performance efficiency compared to the converter with conventional CMOS switch. The proposed circuit has switching frequency of 1.2MHz, 3.3V input voltage, 2.5V output voltage, and maximum current of 100mA. In addition, this paper proposes a SCP (Short Circuit Protection) circuit to ensure reliability.

Design of Power Management Pre-Regulator Using a JFET Characteristic (JFET 특성을 이용한 Power Management IC의 Pre-Regulator 설계)

  • Park, Heon;Kim, Hyoung-Woo;Seo, Kil-Soo;Kim, Young-Hee
    • Proceedings of the KIEE Conference
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    • 2015.07a
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    • pp.1020-1021
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    • 2015
  • 본 논문에서는 상용전압 AC 220V를 인가전압으로 사용하여 PMIC(Power Management IC)의 구동에 적합한 전압을 인가해주는 Pre-Regulator를 설계하였다. 설계된 Pre-Regulator는 상용전압을 사용하기 때문에 Device의 내압이 700V인 Magnachip $0.35{\mu}m$ BCD 공정을 이용하여 설계되었으며, 회로의 구성은 저전압 입력 보호 기능 및 JFET의 구동 제어를 위한 Under Voltage Lock Out(UVLO)회로, 전압조정기(Regulator)의 기준전압을 생성해주는 밴드갭 기준전압 발생(Bandgap Reference)회로, LDO(Low Drop Out)회로로 구성되어있다.

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Time-Domain Analog Signal Processing Techniques

  • Kang, Jin-Gyu;Kim, Kyungmin;Yoo, Changsik
    • Journal of Semiconductor Engineering
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    • v.1 no.2
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    • pp.64-73
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    • 2020
  • As CMOS technology scales down, the design of analog signal processing circuit becomes far more difficult because of steadily decreasing supply voltage and smaller intrinsic gain of transistors. With sub-1V supply voltage, the conventional analog signal processing relying on high-gain amplifiers is not an effective solution and different approach has to be sought. One of the promising approaches is "time-domain analog signal processing" which exploits the improving switching speed of transistors in a scaled CMOS technology. In this paper, various time-domain analog signal processing techniques are explained with some experimental results.

Design of a DC-DC Converter for Portable Device (휴대기기용 DC-DC 부스트 컨버터 집적회로설계)

  • Lee, Ja-kyeong;Song, Han-Jung
    • Journal of Korea Society of Industrial Information Systems
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    • v.22 no.2
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    • pp.71-78
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    • 2017
  • In This Paper, A DC-DC Boost Converter for Portable Device has been Proposed. The Converter Which is Operated with 1 MHz High Switching Frequency is Capable of Reducing Mounting Area of Passive Devices Such as Inductor and Capacitor, Consequently is Suitable for Portable Device. This Boost Converter Consists of a Power Stage and a Control Block and a Protect Block. Proposed DC-DC Boost Converter has been Designed a 0.18 um Magnachip CMOS Process Technology, we Examined Performances of the Fabricated Chip and Compared its Measured Results with SPICE Simulation Data. Simulation Results Show that the Output Voltage is 4.8 V in 3.3 V Input Voltage, Output Current 95 mA Which is Larger than 20~50 mA.

Load-Balance-Independent High Efficiency Single-Inductor Multiple-Output (SIMO) DC-DC Converters

  • Ko, Younghun;Jang, Yeongshin;Han, Sok-Kyun;Lee, Sang-Gug
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.3
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    • pp.300-312
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    • 2014
  • A single-inductor multiple-output (SIMO) DC-DC converter providing buck and boost outputs with a new switching sequence is presented. In the proposed switching sequence, which does not require any additional blocks, input energy is delivered to outputs continuously by flowing current through the inductor, which leads to high conversion efficiency regardless of the balance between the buck and boost output loads. Furthermore, instead of multiple output loop compensation, only the freewheeling current feedback loop is compensated, which minimizes the number of off-chip components and nullifies the need for the equivalent series resistance (ESR) of the output capacitor for loop compensation. Therefore, power conversion efficiency and output voltage ripples can be improved and minimized, respectively. Implemented in a 0.35-${\mu}m$ CMOS, the proposed SIMO DC-DC converter achieves high conversion efficiency regardless of the load balance between the two outputs with maximum efficiency reaching up to 82% under heavy loads.

Implementation of Power Management System for Smart device for the prevention of missing child (미아방지용 스마트 디바이스를 위한 전력 관리 시스템 구현에 관한 연구)

  • Kim, Yuongl-Gil;Kang, Suk-Bum
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2007.10a
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    • pp.493-496
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    • 2007
  • As the ubiquitous society period has set in recently, which resulted from both mass distribution of portable devices such as PDA, PMP, Smart Phones, the demand for more optional features of system and multimedia functions has been increasing. In compliance with thoses needs, the amount of information increased in a system and greater power capacities are needed more than ever. Therefore, in portable device which uses battery as a limited source of power, the power management has become a key factor in the system. This paper concentrates on the Power management solution for Smart device for the prevention of missing child. And ARM9 Core was used as CPU and Windows CE 5.0 was ported to the smart device.

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