• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
• /
• pp.102-104
• /
• 1988

This paper is studied the new speed control system of the DC motor which can drive constant speed at variable load as well as reduce the homonics. System is used thyristor-Leonard circuit with 2-tap in order to reduce the homonics problems due to chopping dc input voltage in chopper system and semiconductor devices in thyristor-Leonard system. There is added to the PLL system to drive the constant speed in variable Load, which has controlled of variable speed in DC motor. Thereby, we have proved its through experiment.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1999년도 하계학술대회 논문집 E
• /
• pp.2434-2437
• /
• 1999

In order to detect the ultrasonic that is generated by the partial discharge of the heavy electric machinery, a Laser Doppler Vibrometer (LDV) was developed. A Michelson type interferometer which employed heterodyne signal process technique was built to measure the frequency and amplitude of vibration. The output signal of the fast photodetector was a frequency modulated signal centered at 40 MHz. The signal from the detector was amplified and downconverted to intermediate frequency centered at 1 MHz after mixing process. The voltage output that was proportional to the velocity of the moving surface(PZT) was obtained using PLL. The spectrum of the FM signal was analyzed and integration method was introduced to obtain amplitude information. This LDV can be used to measure the vibration of MEMS devices, automobiles, HDD and CDP.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1997년도 하계학술대회 논문집 E
• /
• pp.1867-1870
• /
• 1997

A Laser Doppler Vibrometer (LDV) based on the heterodyne method was developed using He-Ne laser as a light source. The heterodyne method was employed to eliminate the ambiguity in the direction of the motion. The frequency shifted object beam (40 MHz) by a Bragg cell was focused on the surface of the moving target and the Doppler shifted reflected beam was combined at the fast photodetector to produce frequency modulated signal centered at 40 MHz. The signal from the detector was amplified, filtered and downconverted to intermediate frequency centered at 5 MHz. The voltage output that was proportional to the velocity of the moving surface was obtained using PLL. This LDV can be used to measure the resonant frequency of the electric equipments such as circuit breakers and bushings, of which resonant frequencies are changed when they are damaged.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2004년도 추계학술대회 논문집 전기기기 및 에너지변환시스템부문
• /
• pp.224-226
• /
• 2004

Digital Kalman filter is presented as a powerful approach to obtain the reference estimation of the control current for shunt active power filter. This algorithm provides the best estimate of the fundamental and harmonic frequency components from the sampled values of the line current or voltage. By adopting of the digital Kalman filtering algorithm, the structure of the control algorithm eliminates the need of a Phase locked loop(PLL) for the synchronization of the reference signal used in the compensation and it not sensitive to the distortion of the line voltage. The effectiveness of the algorithm is confirmed by the computer simulations.

• The Journal of the Acoustical Society of Korea
• /
• 제24권3E호
• /
• pp.109-114
• /
• 2005

In this paper, we present a phase coherent all-digital transceiver for underwater acoustic communication, which allows the system to reduce complexity and increase robustness in time variant underwater environments. It is designed in the digital domain except for transducers and amplifiers and implemented by using a multiple digital signal processors (DSPs) system. For phase coherent reception, conventional systems employed phase-locked loop (PLL) and delay-locked loop (DLL) for synchronization, but this paper suggests a frame synchronization scheme based on the quadrature receiver structure without using phase information. We show experimental results in the underwater anechoic basin at MOERI. The results show that the adaptive equalizer compensates frame synchronization error and the correction capability is dependent on the length of equalizer.

• 한국철도학회:학술대회논문집
• /
• 한국철도학회 2004년도 추계학술대회 논문집
• /
• pp.1480-1485
• /
• 2004

In this paper, a real-time digital kalman filtering algorithm is used to obtain the reference estimation of the control current for shunt active power filter. This algorithm provides the best estimate of the fundamental and harmonic frequency components from the sampled values of the line current or voltage waveform. By adopting of the digital Kalman filtering algorithm, the structure of the control algorithm eliminates the need of a Phase locked loop(PLL) for the synchronization of the reference signal used in the compensation and it not sensitive to the distortion of the line voltage. The effectiveness of the algorithm is confirmed by the computer simulations.

• 제어로봇시스템학회논문지
• /
• 제12권8호
• /
• pp.739-745
• /
• 2006

This paper presents performance improvement of the INS velocity-adided GPS carier tracking loop. To this end, INS velocity-aided GPS carrier tracking loop was modeled as a feedfoward and a feedback loop system. In the phase tracking loop, it was shown that the tracking error caused by the dynamic motion of the vehicle can be compensated with the aiding of the INS information irrespective of the loop order and bandwidth. However, the signal trcking error increases as the INS error increases. It was also shown that in order to remove the tracking error caused by INS bias error, more than or equal to 2nd order PLL should be used. Experiments were carried out and the experimental results were compared with the analysis results.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2006년도 하계종합학술대회
• /
• pp.521-522
• /
• 2006

This paper presents behavioral models using SIMULINK and Verilog-a for a PLL based fractional-N frequency synthesizer. The SIMULINK modeling was built in the frequency-time mixed domain whereas the Verilog-a modeling was built purely in the time domain. The simulated results of the two models were verified to show the same performance within the error tolerance. This top-down design method can provide the readiness for the transistor-level design.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2006년도 하계종합학술대회
• /
• pp.509-510
• /
• 2006

FLL (Frequency Locked Loop) is the core block for high-speed transceiver. It incorporates a PLL for fine locking action, and a coarse controller for coarse locking action. A coarse controller compares frequencies coarsely and is applied to detected frequency difference directly. Compare to conventional FLL, frequency is applied to proposed FLL. Proposed FLL in this paper achieves only 5 cycles for coarse lock and total frequency locking time is 5 times faster than conventional FLL. Thus, proposed FLL is more useful to Ethernet transceiver application that requires high-speed data transfer than conventional FLL. Proposed FLL is based on $0.18{\mu}m$ process.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2006년도 하계종합학술대회
• /
• pp.605-606
• /
• 2006

Voltage Controlled Oscillator(VCO) plays an important role in today's communication systems. Especially, a Clock Generator(CG) in phase-locked loop(PLL) is usually realized by the VCO. This paper proposes a new VCO with a controllable duty cycle buffer, that can be adopted in low-power high-speed communication systems. Delay cell of the VCO is implemented with gilbert cell. Frequency dynamic range of the VCO is in the range of approximately $50MHz{\sim}500MHz$. Parameters with N-well CMOS 0.18-um process with 1.8V supply voltage was used for the simulations.