• Journal of Biomedical Engineering Research
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• v.28 no.3
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• pp.397-409
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• 2007

Owing to needs of biomechanical comprehension and analysis to obtain various medical treatment designs which are related with the spine in order to cure and diagnose LBP patients, the FE modeling and nonlinear analysis of lumbosacrum including a partial ilium and iliolumbar ligaments, were carried out. First, we investigated whether the geometrical configuration of vertebrae displayed by DICOM slice files is regular and normal condition. After constructing spinal vertebrae including a partial ilium, a sacrum and five lumbars (from L1 to L5)with anatomical shape reconstructed using softwares such as image modeler and CAD modeler, we added iliolumbar ligaments, lumbar ligaments, discs and facet joints, etc.. And also, we assigned material property and discretized the model using proper finite element types, thus it was completely modeled through the above procedure. For the verification of each segment, average sagittal ROM, average coronal ROM and average transversal ROM under various loading conditions(${\pm}10Nm$), average vertical displacement under compression(400N), ALL(Anterior Longitudinal Ligament) and PLL(Posterior Longitudinal Ligament) force at L12 level, strains of seven ligaments on sagittal plane at L45 level and maximal strain of disc fibers according to various loading conditions at L45 level, etc., they were compared with experimental results. For the verification of multilevel-lumbosacrum spine including partial ilium and iliolumbar ligaments, the cases with and without iliolumbar ligaments were compared with ROM of experiment. The results were obtained from analysis of the verified FE model as follows: I) Iliolumbar ligaments played a stabilizing role as mainly posterior iliolumbar ligaments under flexion and as both posterior and anterior iliolumbar ligaments of one side under lateral bending. 2) The iliolumbar ligaments decreased total ROM of 1-8% in total model according to various motion conditions, which changed facet contact forces of L5S level by approximately 0.8-1.4 times and disc forces of L5S level by approximately 0.8-1.5 times more than casewithout ilioligaments, under various loading conditions. 3) The force of lower discs such as L45 and L5S was bigger than upper discs under flexion, left and right bending and left and right twisting, except extension. 4) It was predicted that strains of posterior ligaments among iliolumbar ligaments would produce the maximum 16% under flexion and the maximum 10% under twisting. 5) It's expected that this present model applies to the development and design of artificial disc, since it was comparatively in agreement with the experimental datum.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.4
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• pp.117-122
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• 2018

A large-capacity three-phase system air conditioner recently includes an inverter circuit to reduce power consumption. The inverter circuit uses a DC voltage that comes from DC-link power capacitor with the function of rectifying, which means AC voltage to DC voltage using a diode. An electrolytic capacitor is generally used to satisfy the voltage ripple and current ripple conditions of a DC-link power capacitor used for rectifying. Reducing the capacitance of the capacitor decreases the size, weight, and cost of the circuit. This paper proposes an algorithm to reduce the input ripple current by combining the minimum point estimation phase locked loop (PLL) phase control and the average voltage d axis current control technique. When this algorithm was used, the input ripple current decreased by almost 90%. The current ripple of the DC-link capacitor decreased due to the decrease in input ripple current. The capacitor capacity can be reduced but the electrolytic capacitor has a heat generation problem and life-time limitations because of its large equivalent series resistance (ESR). This paper proposes a method to select a film capacitor considering the current ripple at DC-link stage instead of an electrolytic capacitor. The capacitance was selected considering the voltage limitation, RMS (Root Mean Square) current capacity, and RMS current frequency analysis. A $1680{\mu}F$ electrolytic capacitor can be reduced to a $20{\mu}F$ film capacitor, which has the benefit of size, weight and cost. These results were verified by motor operation.

• Progress in Medical Physics
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• v.19 no.1
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• pp.42-48
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• 2008

Bio-implantable devices such as heart pacers, gastric pacers and drug-delivery systems require power for carrying out their intended functions. These devices are usually powered through a battery implanted with the system or are wired to an external power source. This paper describes an inductive power transmission link, which was developed for an implantable stimulator for direct stimulation of denervated muscles. The carrier frequency is around 1MHz, the transmitter coil has a diameter of 46mm, and the implant coil is 46mm. Data transmission to the implant with amplitude shift keying (ASK) and back to the transmitter with passive telemetry can be added without major design changes. We chose the range of coil spacing (2 to 30mm) to care for lateral misalignment, as it occurs in practical use. If the transmitter coil has a well defined and reliable position in respect to the implant, a smaller working range might be sufficient. Under these conditions the link can be operated in fixed frequency mode, and reaches even higher efficiencies of up to 37%. The link transmits a current of 50 mA over a distance range of 2-15 mm with an efficiency of more than 20% in tracking frequency. The efficiency of the link was optimized with different approaches. A class E transmitter was used to minimize losses of the power stage. The geometry and material of the transmitter coil was optimized for maximum coupling. Phase lock techniques were used to achieve frequency tracking, keeping the transmitter optimally tuned at different coupling conditions caused by coil distance variations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.87-93
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• 2010

This paper presents a high resolution, wide input range 2-step time-to-digital converter used in digital PLL. TDC is used to compare the DPLL output frequency with reference frequency and should be implemented with high resolution to improve the phase noise of DPLL. The conventional TDC consists of delay line realized inverters, whose resolution is determined by delay time of inverter and transistor size, resulting in limited resolution. In this paper, 2-step TDC with phase-interpolation and Time Amplifier is proposed to meet the high resolution and wide input range by implement the delay time less than an inverter delay. The gain of Time Amplifier is improved by using the delay time difference between two inverters. It is implemented in $0.13{\mu}m$ CMOS process and the die area is $800{\mu}m{\times}850{\mu}m$ Current consumption is 12 mA at the supply voltage of 1.2 V. The resolution and input range of the proposed TDC are 0.357 ps and 200 ps, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.60-67
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• 2008

A low-power 2.4GHz fractional-N frequency synthesizer has been designed for 2.4GHz ISM band applications such as Bluetooth, Zigbee, and WLAN. To achieve low-power characteristic, the design has been focused on the power optimization of power-hungry blocks such as VCO, prescaler, and ${\Sigma}-{\Delta}$ modulator. An NP-core type VCO is adopted to optimize both phase noise and power consumption. Dynamic D-F/Fs with no static DC current are employed in designing the low-power prescaler circuit. The ${\Sigma}-{\Delta}$ modulator is designed using a modulus mapping circuit for reducing hardware complexity and power consumption. The designed frequency synthesizer which was fabricated using a $0.18{\mu}m$ CMOS process consumes 7.9mA from a single 1.8V supply voltage. The experimental results show that a phase noise of -118dBc/Hz at 1MHz offset, the reference spur of -70dBc at 25MHz offset, and the channel switching time of $15{\mu}s$ over 25MHz transition have been achieved. The designed chip occupies an area of $1.16mm^2$ including pads where the core area is only $0.64mm^2$.

• The Journal of the Korea Contents Association
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• v.10 no.2
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• pp.72-80
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• 2010

The 1Gbps clock and data recovery (CDR) circuit using the proposed multi-point phase detector (PD) is presented. The proposed phase detector generates up/down signals comparing 3-point that is data transition point and clock rising/falling edge. The conventional PD uses the pulse width modulation (PWM) that controls the voltage controlled oscillator (VCO) using the width of a pulse period's multiple. However, the proposed PD uses the pulse number modulation (PNM) that regulates the VCO with the number of half clock cycle pulse. Therefore the proposed PD can controls VCO preciously and reduces the jitter. The CDR circuit is tested using 1Gbps $2^{31}-1$ pseudo random bit sequence (PRBS) input data. The designed CDR circuit shows that is capable of recovering clock and data at rates of 1Gbps. The recovered clock jitter is 7.36ps at 1GHz and the total power consumption is about 12mW. The proposed circuit is implemented using a 0.18um CMOS process under 1.8V supply.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.2
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• pp.25-34
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• 2010

This paper proposed a high-speed voltage-controlled ring-oscillator(VCRO) using a frequency doubling technique. The design of the proposed oscillator has been based on TSMC 0.18um 1.8V CMOS technology. The frequency doubling technique is achieved by AND-OR operations with 4 signals which have $90^{\circ}$ phase difference one another in one cycle. The proposed technique has been implemented using a 4-stage differential oscillator compose of differential latched inverters and NAND gates for AND and OR operations. The differential ring-oscillator can generate 4 output signals, which are $90^{\circ}$ out-of-phase one another, with low phase noise. The ANP-OR operations needed in the proposed technique are implemented using NAND gates, which is more area-efficient and provides faster switching speed than using NOR gates. Simulation results show that the proposed, VCRO operates in the frequency range of 3.72 GHz to 8 GHz with power consumption of 4.7mW at 4GHz and phase noise of ~-86.79dBc/Hz at 1MHz offset. Therefore, the proposed oscillator demonstrates superior performance compared with previous high-speed voltage-controlled ring-oscillators and can be used to build high-performance frequency synthesizers and phase-locked loops for radio-frequency applications.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.2
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• pp.72-77
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• 2009

In this paper, a 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial data communication without the reference clock is described This CDR circuit consists of 5 parts as Phase and frequency detector(PD and FD), multi-phase Voltage Controlled-Oscillator(VCO), Charge-pumps (CP) and external Loop-Filter(KF). It is adapted the PD and FD, which incorporates a half-rate bang-bang type oversampling PD and a half-rate FD that can improve pull-in range. The VCO consists of four fully differential delay cells with rail-to-rail current bias scheme that can increase the tuning range and tuning linearity. Each delay cell has output buffers as a full-swing generator and a duty-cycle mismatch compensation. This materialized CDR can achieve wide pull-in range without an extra reference clock and it can be also reduced chip area and power consumption effectively because there is no additional Phase Locked- Loop(PLL) for generating reference clock. The CDR circuit was designed for fabrication using 0.18um 1P6M CMOS process and total chip area excepted LF is $1{\times}1mm^2$. The pk-pk jitter of recovered clock is 26ps at 3.2Gb/s input data rate and total power consumes 63mW from 1.8V supply voltage according to simulation results. According to test result, the pk-pk jitter of recovered clock is 55ps at the same input data-rate and the reliable range of input data-rate is about from 2.4Gb/s to 3.4Gb/s.

• Polymer(Korea)
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• v.30 no.5
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• pp.445-452
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• 2006

In this study, we investigated interaction of Schwann cells (SCs) with various cell-adhesive coated polymer surface. We used cell-adhesives that like a fibronectin (FN), fibrinogen(FG), laminin(LM), vitronectin (VN), poly-D-Iysine (PDL), and poly-L-Iysine (PLL) to coat PLGA film surface and evaluated the surface property of coated or not PLGA films by measurement of water contact angle and ESCA. SCs were cultured on coated or non-coated PLGA film surface, and then examined the cell adhesion and proliferation by cell count and SEM observation. Cell count results revealed initial cell adhesion related to protein adsorption on PLGA surface. In addition, serum content in media related to cell proliferation rate. In this result, we recognized that adhesion and proliferation of SCs were affected by specific cell-adhesives. In these results, we recognized that is important to provide the suitable surface environment according to cell types and culture condition for improvement of cell adhesion and proliferation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.4
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• pp.381-388
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• 2015

In this paper, a wireless video streaming system is designed and implemented for TV white space applications. It consists of a RF transceiver module, a digital modem, a camera, and a LCD screen. A VGA resolution video is captured by a camera, modulated by modem, and transmitted by RF transceiver module, and finally displayed at a destination 2.6-inch LCD screen. The RF transceiver is based on direct-conversion architecture. Image leakage is improved by low pass filtering LO, which successfully covers the TVWS. Also, DC offset problem is solved by current steering techniques which control common mode level at DAC output node. The output power of the transmitter and the minimum sensitivity of the receiver is +10 dBm and -82 dBm, respectively. The channel bandwidth is tunable among 6, 7 and 8 MHz according to regulations and standards. Digital modem is realized in Kintex-7 FPGA. Data rate is 9 Mbps based on QPSK and 512ch OFDM. A VGA video is successfully streamed through the air by using the developed TV white-space RF communication module.