• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.1
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• pp.46-52
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• 1985

The modulo PLL was applied to the implementation of frequency synthesis with the narrow channel spacing, many channels and three different frequency bands. So , VCO (voltage controlled oscillator) designed In this paper is suitable for the device with three different frequency bands 10Hz, 40Hz, 400Hz channel spacing, and 512 channels.

• Journal of Electrical Engineering and Technology
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• v.11 no.6
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• pp.1707-1713
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• 2016

This paper proposes a dc error compensation algorithm using dq-synchronous coordinate transform digital phase-locked-loop in single-phase grid-connected converters. The dc errors are caused by analog to digital conversion and grid voltage during measurement. If the dc offset error is included in the phase-locked-loop system, it can cause distortion in the grid angle estimation with phase-locked-loop. Accordingly, recent study has dealt with the integral technique using the synchronous reference frame phase-locked-loop method. However, dynamic response is slow because it requires to monitor one period of grid voltage. In this paper, the dc offset error compensation algorithm of the improved response characteristic is proposed by using the synchronous reference frame phase-locked-loop. The simulation and the experimental results are presented to demonstrate the effectiveness of the proposed dc offset error compensation algorithm.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.3
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• pp.141-144
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• 2015

A broadband radio frequency synthesizer for multi-band, multi-standard mobile DTV tuners is proposed, it's loop bandwidth can be calibrated to optimize integrated phase noise performance without the problem of phase noise peaking. For this purpose, we proposed a new third-order scalable loop filter and a scalable charge pump circuit to minimize the variation in phase margin during calibration. The prototype phase-lock loop is fabricated in 180nm complementary metal-oxide semiconductor shows that it effectively prevents phase noise peaking from growing while the loop bandwidth increases by up to three times.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2007.11a
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• pp.279-285
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• 2007

Since the residential load is an AC load and the output of solar cell is a DC power, the photovoltaic system needs the DC/AC converter to utilize solar cell. In case of driving to interact with utility line, in order to operate at unity power factor, converter must provide the sinusoidal wave current and voltage with same phase of utility line. Since output of solar cell is greatly fluctuated by insolation, it is necessary that the operation of solar cell output in the range of the vicinity of maximum power point. In this paper, DC/AC converter is three phase PWM converter with smoothing reactor. And then, feedforward control used to obtain a superior characteristic for current control and digital PLL circuit used to detect the phase of utility line.

• Journal of the Korean Institute of Telematics and Electronics
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• v.10 no.6
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• pp.25-44
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• 1973

The please relation between motive force and result is reviewed in view point of the correlation function as well as the redundancy in a continuous signal which permits the sampled treatment. A new correlation function (to be named Time Dependent Correlation Function) which is a functon of time, is defined in order to indicate the variation of the correlation between two signals. As application a phase looked loop is analysed which shows the increase of correlation between input signal and output signal of the loop after the application of the input signal. Finally again the T.D.Correlation Function method is used to show how the polyphase envelope detection-method is justifiable by this method.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.55 no.8
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• pp.399-403
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• 2006

An accurate constant output voltage provided by the analog memory cell may be used by the low power oscillator to generate an accurate low frequency output signal. This accurate low frequency output signal may be used to maintain long-term timing accuracy in host devices during sleep modes of operation when an external crystal is not available to provide a clock signal. Further, incorporation of the analog memory cell in the low power oscillator is fully implementable in a 0.35um Samsung standard CMOS process. Therefore, the analog memory cell incorporated into the low power oscillator avoids the previous problems in a oscillator by providing a temperature-stable, low power consumption, size-efficient method for generating an accurate reference clock signal that can be used to support long sleep mode operation.

• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.55-58
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• 2000

본 논문에서는 제한된 통신 채널의 대역에서 주파수 효율이 높은 OFDM 시스템을 위한 반송파 주파수 동기 알고리즘을 제안한다. OFDM 시스템에서의 반송파 주파수 옵셋은 부반송파 간격의 정수배와 소수배로 나누어진다 소수배 주파수 옵셋이 ± 0.5 근처의 값을 가질 경우에는 정확한 정수배 주파수 옵셋 추정이 어렵고 반송파 동기 PLL이 소수배 주파수 옵셋을 추적하는데 많은 시간이 소요된다. 제안한 알고리즘은 정수배 주파수 옵셋을 제거하기 위해 2개의 심볼 만을 이용하고 다중경로 패널에서도 정확한 정수배 주파수 옵셋의 추정이 가능하다 또한, 소수배 주파수 옵셋이 ± 0.5 근처의 값을 가질 경우 적은 계산량으로 주파수 옵셋을 ± 0.1 이내로 보상할 수 있다.

• Journal of Korea Society of Industrial Information Systems
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• v.12 no.2
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• pp.79-84
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• 2007

This papar reports design and fabrication of CMOS temperature control circuit using MOSIS 0.25um-3.3V CMOS technology. The proposed circuit has a temperature coefficient of $13mV/^{\circ}C$ for a wide operating temperature range with a good linearity. Furthermore, the temperature coefficient of output voltage can be controlled by adjusting external bias voltage. This circuit my be applicable to the design of one-chip IC where quartz crystal resonator is mounted on CMOS oscillator chips.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.107-110
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• 2005

This paper describes the design and fabrication of synchronous clock recovery module for S-DMB Gap Filler. Using the 2.304MHz TTL signal from gap filler tuner, clock recovery module with 10MHz output frequency including holdover function is designed. The measured performance of the clock recovery module shows a stability of less than 0.01ppm, 29 sec stability time, 10 sec holdover time, and maximum -113dBc/Hz@100Hz phase noise.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.33-39
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• 2013

There have been studies in improving jitter characteristic of delay locked loop (DLL) even it has a shorter jitter that of phase locked loop (PLL). These studies result in numerous architectures of DLL which improve jitter performance. The paper shows that the jitter characteristic can be improved with various loop filters in DLL. It has been designed with 1.8V $0.18{\mu}m$ CMOS process.