• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.336-339
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• 1999

In this paper, we describe the accommodation of the PRML technique for the high speed and high density optical disk systems, which has been very effective in the high density HDD systems. To make the PRML technique adequate for the optical disk systems, the channel modeling and the simulation are performed. Finally, the architecture has been designed and realized into an ASIC. We have focused on the differences of PRML architecture between the HDD system and the optical disk system, and the digital realization of the PLL which has been realized with analog circuits.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.10
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• pp.73-81
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• 1994

It is AGC(Automatic Gain Control) amplifier to decide characteristics of IF(Intermediate Frequency) processing IC. When demodulated IF signal by PLL type demodulator, the amplitude of input singla should be maintained at a certain amplitude. The AGC amplifier is an important factor to achieve this condition. The AGC amplifier needs the wide dynamic range, the wide AGC range and better noise characteristics. We designed the AGC amplifier to satisfy these characteristics.

• Proceedings of the KSR Conference
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• 2005.05a
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• pp.895-902
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• 2005

This paper presents contactless power transfer system for an electric railway system which makes use of electromagnetic induction among the coils. A full bridge type series resonant inverter is used as a power conversion system. and MC14046 PLL of Motorola is used as a control device. Finally, presented system is verified by simulation.

• Proceedings of the IEEK Conference
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• 2000.06e
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• pp.89-92
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• 2000

A wire communication module for PLC controller was developed. This system consists of RF module interface part, RS232 serial communication control part, LED display part and control S/W with GUI interface. RF communication frequency is controlled by PLL controlling and communication rate is also controlled as 1200 and 4800 bps. Communication and control status are displayed on LED. As a S/W part, graphic user interface on Window 95 O.S. was developed. To show the validity of the developed system, severial communication and control of PLC system were experemented.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.8
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• pp.52-59
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• 1998

New types of PFD (phase-frequency detector) are proposed with reset time and propagation delay reduced. The perfomrance of our proposed PFDs are confirmed by SPICE simulation with 0.8.mu.m CMOS process parameter. As a result of simulation, the reset time of PFDs are 0.32 nsec and 0.030 nsec in capture-process. The proposed PFDs can be used in hihg-speed phase-licked loop (PLL).

• Proceedings of the KIEE Conference
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• 1987.11a
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• pp.86-89
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• 1987

This paper treats with the design and fabrication of a frequency synthesizer for the generation of intermediate frequency of a HF band transceiver. The synthesizer is designed to control frequencies using a phase-locked loop and it is shown that method improved the performance of frequency accuracy and locking time then that of the crystal-reference system.

• The Journal of the Acoustical Society of Korea
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• v.5 no.2
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• pp.13-18
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• 1986

디지틀 데이터 전송시 수신기에서 또는 중계기에서 송신 데이터를 구하기 위해서는 타이밍 클럭 을 복원해야 한다. 대개의 실장된 경우에서는 PLL을 이용하는데, 이때 시스템/랜덤 지터가 발생되고 또 중계기가 늘어남에 따라서 생성된 지터가 누적되는데 이것을 해석하였다. 90 Mbps 광통신 시스템에 적 용하여 테이블 1,2,3,4와 같은 결과를 얻었으며, 시스템 지터가 랜덤 지터보다 더 급격히 누적됨을 알았 고, 또한 댐핑팩터가 커짐에 따라 지터 누적이 양화됨을 알았다.

• Proceedings of the KIEE Conference
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• 1997.07a
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• pp.146-148
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• 1997

This paper investigates the position sensorless control of switched reluctance motor. The system consists of the position detection circuit by the new phase detection algorithm, digital logic commutator, PLL for speed control and 4-phase inverter. The performances in the proposed system are verified through the experiment.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.653-654
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• 2006

A Pre-emphasis transmitter for DRAM bus system has achieved 3.2Gbps/pin operation at 1.8V supply voltage with 0.18um CMOS process. The transmitter has 800MHz PLL to generate 4 phase clocks. The 4 phase clocks are used for input clock of PRBS and multiplexing. One tap pre-emphasis is used to reduce inter symbol interference (ISI) caused by channel low pass effects. The analog calibration makes the optimized driver impedance independent with the PVT variation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.270-274
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• 2002

본 논문은 고속 무선랜에 적용하고 있는 OFDM시스템에서 국부발진기의 위상잡음에 의해서 기저대역의 채널에서 나타나는 위상변위특성을 해석하고, 국부발진기를 포함하는 PLL시스템에서 위상잡음 변화를 수치적인 해석을 하였다. OFDM신호를 QPSK, 16QAM 변조신호로 전송하였을 경우, 위상잡음에 따른 관계를 변조신호의 성상도 및 BER관계로써 분석하였다.