• Journal of the Microelectronics and Packaging Society
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• v.9 no.1
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• pp.15-20
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• 2002

In this project, we hale developed various techniques for subminiaturization, surface implementation, high frequency design, small-size SMD, performance test and application of the Dual PLL module, which is a core component for the personal communication systems. We also obtained base techniques for the next-generation Dual PLL module design and fabrication techniques for an internationally competitive subminiature Dual PLL module.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.11a
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• pp.230-235
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• 1999

In this paper, Using third-order system of the PLL we analyze the aspect of flicker noise appearing troubles In the low frequency band. Since i. Is difficult to analyze mathematically flirter noise In the third-order system of the PLL, introducing the concept of pseudo-damping factor using the optimized second-filter makes an ease of the access of the flicker-noise variance. we'll show a numerical formula of flicker variance in the third-order system of the PLL which is compared with that of 1/f-noise variance in the second-order system of the PLL.

• Proceedings of the KIPE Conference
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• 2014.07a
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• pp.281-282
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• 2014

본 논문은 FPGA 기반의 DSC-PLL(Delayed Signal Cancellation - Phase Locked Loop)을 설계하고, 왜곡된 3상전압 조건에서 위상추종결과를 비교실험 하였다. FPGA 구현 알고리즘은 Matlab/Simulink와 연동된 System Generator를 이용하여 DSC-PLL 모델을 설계하고, Verilog HDL 코드로 변환 하였다. 불평형 및 고조파를 포함한 왜곡된 3상 전압 조건에서 FPGA에 구현된 DSC-PLL과 SRF-PLL (Synchronous Reference Frame - Phase Locked Loop)의 d-q축 고조파 감쇠특성 및 위상추종능력을 실험을 통해 비교하였다. DSC-PLL은 약 5.44ms 이내에 d-q축 고조파 성분을 제거함으로써 정상분 기본파 전압의 위상을 빠르게 추종하는 것을 검증하였다.

• Journal of the Korea Safety Management & Science
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• v.17 no.3
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• pp.377-381
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• 2015

For the first time, PLL frequency synthesizer using DDS was adapted for the data link communication system which should fast transmit and receive each other with the correct information and fast Hopping System. It is inevitable to lost the synchronization by slow lock time about PLL and no cut off the noise. This paper propose the design of PLL frequency synthesizer which can make 800MHz frequency range. The PLL frequency synthesizer has three high qualities those are frequency accuracy, fast lock time and outstanding phase noise.

• Proceedings of the KIEE Conference
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• 2006.10d
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• pp.226-228
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• 2006

This paper presents a comparative study of single-phase PLL algorithms using virtual 2-phase strategy. Simulation and experimental results, including operation of the PLL structures introduced in reference papers, are presented to allow a performance comparison of the PLL algorithms.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.368-371
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• 2000

The PLL(Phase-Locked Loop) techniques re employed to make the switching frequency of a resonant inverter follow the resonant frequency which may vary due to the load variations during operation. The conventional design guide of PLL is not suitable in these case since the inverter characteristics are not considered. In this paper the phase characteristics of a resonant inverter is analysed and added to the closed loop. And the design of PLL with digital phase detector is illustrated for the output frequency to track the resonant frequency of the inverter.

• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.508-509
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• 2012

그리드 연계 인버터의 주파수 위상 동기를 위해 사용하는 SRF PLL의 입력함수를 Vq및 Vd 전압을 복합적으로 사용하여 응답특성을 개선시켰다. 기존의 SRF PLL에서 Vq만을 이용한 구조는 위상범위 [$-{\pi}/2$, ${\pi}/2$]에서만 선형 동작이 가능하지만, 제안된 구조는 $2{\pi}$ 영역 모두에서 선형 동작이 가능토록 하였다. 시뮬레이션으로 위상차 ${\pi}$에서 기존 SRF PLL의 부동작을 확인하고 제안된 방법의 속응성을 보였다.

• 전기의세계
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• v.30 no.12
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• pp.832-837
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• 1981

The study of PLL System to control the Speed of three phase induction motor is described. By solving some problems of conventional PLL system, the system has ability to be easily locked under any conditions. In order to study response velocity and stability of system, this paper presents different filter types and methods of determination of time constant.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.11
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• pp.76-85
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• 1997

Charge-pump loop filter was designed using GaAs MESFET for GHz-range PLL system applications. Characteristics of charge-pump loop filter and stability of charge-pump PLL, system were analyzed. Performance specifications were defined and a charge-pump loop filter was designed that satisfies these specifications.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.11
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• pp.1447-1454
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• 2018

In this paper, the design of robust DSC-PLL(Delayed Signal Cancellation Phase Locked Loop) is proposed for coping with frequency variation. This method shows significant performance for detection of fundamental positive sequence component voltage when the grid voltage is polluted by grid unbalance and frequency variation. The feedback frequency estimation of DSC-PLL is tracking the drift in the phase by unbalance and frequency variation. The robust DSC PLL is to present the analysis on method and performance under frequency variations. These compensation algorithms can correct for discrepancies of changing the frequency within maximum 193[ms] and improve traditional DSC-PLL. Linear interpolation method is adopted to reduce the discretized errors in the digital implementation of the PLL. For verification of robust characteristic, PLL methods are implemented on FPGA with a discrete fixed point based. The proposed method is validated by both Matlab/Simulink and experimental results based on FPGA(XC7Z030).