• Proceedings of the Optical Society of Korea Conference
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• 1991.06a
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• pp.190-193
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• 1991

The monolithically integrated receiver OEIC using InGaAs/InP PIN PD, junction FET's and bias resistor has been fabricated on semi-insulating InP substrate. The fabrication process is highly compatible between PD and self-aligned JFET, and reduction in gate length is achieved using an anisotropic selective etching and a non-planar OMVPE process. The PIN photodetector with a 80 ${\mu}{\textrm}{m}$ diameter exhibits current of less than 5 nA and a capacitance of about 0.35 pF at -5 V bias voltage. An extrinsic transconductance and a gate-source capacitance of the JFET with 4 ${\mu}{\textrm}{m}$ gate length (gate width = 150 ${\mu}{\textrm}{m}$) are typically 45 mS/mm and 0.67 pF at 0 V, respectively. A voltage gain of the pre-amplifier is 5.5.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.270-273
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• 2000

We have fabricated and analyzed photodiodes for optical link with Si pin structures. As the results of experiment, the web patterned photodiode(type C) with $p^{+}$-guard ring showed low junction capacitance of 6~7 pF at $V_{R}$=-5V and high separation ability for optical signal(dark current : $\leq$ 5 nA, optical signal current : $\geq$ 340 nA) due to the small effective $p^{+}$-n junction area and the expanded electric field region. The fabricated Si pin photodiode can be applicable for detecting an optical signal with the wavelength of about 660~670 nm. It can also be integrated with the twin well CMOS structure to develope an one chip based optical receiver IC. IC.C.

• ETRI Journal
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• v.30 no.4
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• pp.612-614
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• 2008

A novel linear switched termination active cross-coupled low-voltage differential signaling (LVDS) transceiver operating at 1.5 GHz clock frequency is presented. On the transmitter side, an active cross-coupled linear output driver and a switched termination scheme are applied to achieve high speed with low current. On the receiver side, a shared pre-amplifier scheme is employed to reduce power consumption. The proposed LVDS transceiver implemented in an 80 nm CMOS process is successfully demonstrated to provide a data rate of 6 Gbps/pin, an output data window of 147 ps peak-to-peak, and a data swing of 196 mV. The power consumption is measured to be 4.2 mW/pin at 1.2 V.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.165-168
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• 2002

As the demand for higher data-rate chip-to-chip communication such as memory-to-controller, processor-to-processor increases, low cost high-speed serial links\ulcorner become more attractive. This paper describes a 0.25-fm CMOS 1.6Gbps/pin 4-level transceiver using Stub Series Terminated Logic for high Bandwidth. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by channel low pass effects, process-limited on-chip clock frequency, and serial link distance. The proposed transceiver uses multi-level signaling (4-level Pulse Amplitude Modulation) using push-pull type, double data rate and flash sampling. To reduce Process-Voltage-Temperature Variation and ISI including data dependency skew, the proposed high-speed calibration circuits with voltage swing controller, data linearity controller and slew rate controller maintains desirable output waveform and makes less sensitive output. In order to detect successfully the transmitted 1.6Gbps/pin 4-level data, the receiver is designed as simultaneous type with a kick - back noise-isolated reference voltage line structure and a 3-stage Gate-Isolated sense amplifier. The transceiver, which was fabricated using a 0.25 fm CMOS process, performs data rate of 1.6 ~ 2.0 Gbps/pin with a 400MHB internal clock, Stub Series Terminated Logic ever in 2.25 ~ 2.75V supply voltage. and occupied 500 * 6001m of area.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.1
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• pp.108-111
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• 2016

We propose the method for measuring sensitivity of optical receiver of a long-range laser range finder in real-time. The sensitivity of the detector can be calculated using the detected voltage of the reference sensor, the area of the reference sensor and the transmittance ratio of neutral density filters. To evaluate the performance of the proposed method, we implemented a system and performed experiments. As a result, this system can be measured from 2nW to $113{\mu}W$. With this system, we measured the sensitivity of 37nW and 7nW with PIN PD and APD sample, respectively. This system has the advantage for the performance test of an optical sensor module in the long-range laser range finder.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.2
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• pp.220-228
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• 2012

In this paper, we explained the design technique about Ka-band active limiter for protecting the receiver of a millimeter wave seeker. To implement low flat leakage power, we proposed the control circuit of active limiter to control limiter voltage with PRF(Pulse Repetition Frequency) signal and input power. This active limiter consisted of the conventional 2 stage passive limiter, a feedback circuit with a directional coupler, detector, non-inverting amplifier and over-current protection resistance. As the test result of the fabricated Ka-band limiter, it had 1 GHz bandwidth, 3.5 dB insertion loss at the small input power and -7.5 dBm flat leakage at the 4 W RF input power, respectively.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.4
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• pp.45-53
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• 1999

A pre amplifier, a limiting amplifier, and a decision IC chipset for 10Gbit/s optical receiver was implemented with AIGaAs/GaAs HBT(Heterojunction Bipolar Transistor) technology. The HBT allows a cutoff frequency of 55GHz and a maximum oscillation of 45GHz. An optical receiver front-end was implemented with the fabricated pre amplifier IC and a PIN photodiode. It showed 46dB$\Omega$, gain and $f_{3db}$ of 12.3GHz. The limiting amplifier Ie showed 27dB small signal gain, $f_{3db}$ of 1O.6GHz, and the output is limited to 900mVp-p from 20mVp-p input voltage. The decision circuit IC showed 300-degree phase margin and input voltage sensitivity of 47mVp-p at 1OGbit/s.

• Journal of Advanced Marine Engineering and Technology
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• v.39 no.1
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• pp.63-67
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• 2015

White light-emitting diode (WLED) is growing interest in using both illumination and communications. This paper reports visible light communication (VLC) composed of a super bright white light-emitting diode, low cost commercial photo-diode and a Fresnel lens. LED driver is consisted of the power MOSFET and MOSFET driver that switches the LED on and off. The modulation bandwidth of the LED used was determined to be 8 MHz. However, it was possible to communicate up to 1 Mbps under illumination of 500 lx because of the weak signal power and a low spectral sensitivity of the SHF213 as a PIN photodiode. In order to enhance the system bandwidth, the LED light was focused on the PIN photodiode by use of the Fresnel lens. As a result of that, visible light link was operated up to modulation bandwidth of the LED. The signal to noise ratio can be improved by 40 dB using an optical concentration at the receiver.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.7
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• pp.1210-1218
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• 2001

In this paper, A X-band voltage-controlled hair-pin resonator oscillator(VCHRO) is able to a local oscillator or a signal source in transmitter/receiver of a microwave communication system for mobile radar, is designed and fabricated In order to apply mobile radar system is used the hair-pin resonator stronger on shock or vibration than the dielectric resonator, and also, in order to improvement the phase noise and output power is used a system of serial feedback format A hair-pin resonator was simulated by momentum method of HP ADS and then a oscillator circuit was designed that operates at 10.525 GHz by nonlinear method in harmonic balance simulation. The HRO generated output power of 6.93 dBm at 10.525 GHz, phase noise of -57.74 dBc at 100 kHz offset from carrier and the 2'nd harmonic was suppressed -23.90 dBc.

• ETRI Journal
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• v.27 no.1
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• pp.81-88
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• 2005

In this paper, interface circuits that are suitable for point-to-point interconnection with an over 1 Gbps data rate per pin are proposed. To achieve a successful data transfer rate of multi-gigabits per-second between two chips with a point-to-point interconnection, the input receiver uses an on-chip parallel terminator of the pass gate style, while the output driver uses the pullup and pulldown transistors of the diode-connected style. In addition, the novel dynamic voltage level converter (DVLC) has solved such problems as the access time increase and valid data window reduction. These schemes were adopted on a 64 Mb DDR SRAM with a 1.5 Gbps data rate per pin and fabricated using a 0.10 ${\mu}m$ dual gate oxide CMOS technology.