• Title/Summary/Keyword: PFC(Power-Factor-Correction)

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A Design of PFC Circuit for Reducing the Harmonic in Constant Voltage-fed Electronic Ballast Circuit (정전압형 전자식 안정기 회로의 고조파 저감을 위한 PFC회로의 설계)

  • 이현우;이현무;고강훈;고희석
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.18 no.4
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    • pp.41-48
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    • 2004
  • In this paper, a PFC(Power Factor Correction) electronic ballast with constant voltage-fed is proposed. The proposed PFC electronic ballast is combined of a high-efficiency boost converter and a conventional half bridge inverter. It is proved that the ripple of input-current and the input-current's harmonic of the proposed PFC electronic ballast are reduced using the voltage divider and soft-switching technique. It is demonstrated that simulation results for fluorescent lamp correspond with theoretical analysis.

Single-Phase SRM Driving Method for Power Factor Correction (단상 SRM의 역률 개선을 위한 구동방식)

  • Ahn Jin-Woo;Park Sung-Jun;Son Ick-Jin;Oh Seok-Gyu;Hwang Young-Moon
    • Proceedings of the KIPE Conference
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    • 2001.07a
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    • pp.235-238
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    • 2001
  • A novel single-stage power factor corrected (PFC) drive for switched reluctance motor (SRM) is presented to achieve sinusoidal, near unity power factor input current. The proposed PFC SRM drive has no additional active switch. And a single-stage approach, which combines a DC link capacitor used as dc source and a drive used for driving the motor into one power stage, has a simple structure and low cost. The characteristics and validity of the proposed circuit will be discussed in depth through the experimental results.

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Off-time Control Method for High Power Density AC/DC Adapter (고전력밀도 AC/DC Adapter를 위한 off-time 제어법)

  • Kang, Shin-Ho;Jang, Jun-Ho;Hong, Sung-Soo;Lee, Jun-Young
    • The Transactions of the Korean Institute of Power Electronics
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    • v.12 no.6
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    • pp.510-516
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    • 2007
  • The proposed method offers an improved control method for high power density AC/DC adapter by using more energy efficient electrical equipments. Power factor correction (PFC) topology is based on boost topology with boundary conduction mode (BCM). DC/DC topology is based on half-bridge topology with fixed 50% duty and newly introduced off-time control method, which helps to reduce size of the semiconductor and the magnetic devices. Test results with 85W AC/DC adapter (18.5V/4.6A) design show that the measured efficiency is 90% with power density of $36W/in^3$. It also shows low no load power consumption of about 0.5W.

A Study on the Power Supply System for the Arc Lamp (아크램프를 위한 전원공급 시스템의 연구)

  • La, Jae Du
    • The Transactions of the Korean Institute of Electrical Engineers P
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    • v.67 no.3
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    • pp.125-130
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    • 2018
  • Arc lamps are now widely utilized as illumination sources for a large number of investigations in wide-field fluorescence microscopy. Among many power converters for the lamp, the PSFB (Phase-Shift Full-Bridge) converter with the ZVS (Zero Voltage Switching) is the most widely used soft switched circuit in high-power applications. Also, in the most luminaries, the power factor has to be more and more important. Thus, the power factor correction(PFC) must be included in the power system. A new igniter module using the switching power device and the transformer is proposed instead of the conventional igniter using the mechanical contactor. The proposed converter with the high power factor and high efficiency is verified through the experimental works.

New Single Stage PFC Full Bridge Converter (새로운 단일전력단 역률보상 풀브리지 컨버터)

  • 임창섭;권순걸;조정구;송두익
    • The Transactions of the Korean Institute of Electrical Engineers B
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    • v.52 no.12
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    • pp.655-660
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    • 2003
  • This paper proposes new single stage power factor correction (PFC) full bridge converter. The proposed converter is combined previous ZVS full bridge DC/DC converter with two inductors, two diodes, two magnetic coupling transformer for PFC. This process of power is isolated from the source and also regulate stable DC output voltage in a category. In this topology, the voltage stress of main switches is reduced by zero voltage switching. Moreover, the proposed converter doesn't need active PFC switch and auxiliarly circuits, like control and gating board, so it could decrease the size and cost and increase the efficiency.

Digital Implementation methode of Totem-pole PFC using GaN Transistor (GaN 트랜지스터를 적용한 토템폴 역률개선회로의 디지털 구현방법)

  • Kwak, Bongwoo;Kim, Myungbok
    • Proceedings of the KIPE Conference
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    • 2019.11a
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    • pp.120-121
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    • 2019
  • 본 논문은 GaN 트랜지스터를 적용한 토템폴 PFC(Power Factor Correction)의 디지털 구현을 위한 방법을 제시한다. 특히, GaN 트랜지스터의 낮은 역회복 특성으로 토템폴 PFC의 연속 연속 모드 동작을 가능하게 한다. 토템폴 PFC는 고속 스위칭을 하는 레그를 GaN 트랜지스터를 사용하고, 라인 주파수로 스위칭 하는 레그는 일반적인 MOSFET을 사용하게 된다. 구조적으로 토템폴 PFC는 제로 크로싱에서 전류 스파이크 문제가 발생한다. GaN 트랜지스터는 전류 스파이크에 취약하기 때문에 최소화되어야 한다. 따라서, 본 논문은 디지털 구현에 있어 제로 크로싱에서 소프트 스타트 구현을 통해 이 문제를 최소화 하고, 모의실험을 통해 디지털 구현의 타당성을 입증하였다.

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Analysis on the start-up mode in PFC converter (PFC 컨버터의 초기 동작에 대한 연구)

  • Kim, Jin-Un;Lee, Sang-Hyeok;Gong, Sang-Ho
    • Proceedings of the KIPE Conference
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    • 2015.07a
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    • pp.469-470
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    • 2015
  • 본 논문에서는 PFC(Power Factor Correction) 컨버터의 초기 구동시 발생하는 돌입전류 문제 및 스위치의 고장을 진단하는 방법에 대해 기술한다. PFC 컨버터는 초기 구동시 출력단의 대용량 커패시터에 의해 높은 돌입전류가 발생하여 시스템 손상 및 전력 계통의 품질과 고조파를 발생하는 문제점을 갖고 있다. 따라서 본 논문에서는 저항과 스위치를 이용한 PFC 컨버터의 초기 돌입 전류 제한 및 안정적인 동작을 위한 스위치 고장진단 방법을 제안하고, 시뮬레이션을 통해 타당성을 입증하였다.

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A New Zero-Voltage-Switching Bridgeless PFC, Using an Active Clamp

  • Ramezani, Mehdi;Ghasedian, Ehsan;Madani, Seyed M.
    • Journal of Power Electronics
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    • v.12 no.5
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    • pp.723-730
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    • 2012
  • This paper presents a new ZVS single phase bridgeless (Power Factor Correction) PFC, using an active clamp to achieve zero-voltage-switching for all main switches and diodes. Since the presented PFC uses a bridgeless rectifier, most of the time, only two semiconductor components are in the main current path, instead of three in conventional single-switch configurations. This property significantly reduces the conduction losses,. Moreover, zero voltage switching removes switching loss of all main switches and diodes. Also, auxiliary switch turns on zero current condition. The presented converter needs just a simple non-isolated gate drive circuitry to drive all switches. The eight stages of each switching period and the design considerations and a control strategy are explained. Finally, the converter operation is verified by simulation and experimental results.

Double Step-Up PFC Converter Using Asymmetrical PWM Scheme (비대칭 PWM 방식을 이용한 이중 승압 기능을 갖는 PFC 컨버터)

  • Yeongjin Kim;Jaeseong Lim;Honnyong Cha
    • The Transactions of the Korean Institute of Power Electronics
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    • v.28 no.1
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    • pp.8-14
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    • 2023
  • This paper proposes a PFC converter with a double step-up function using an asymmetrical PWM scheme. For the conventional PWM scheme, the input voltage range, which maintains a double step-up function, is limited because the proposed converter has different voltage gains and characteristics when the duty ratio(D) is less than 0.5. The proposed converter has a constant voltage gain regardless of the magnitude of the input voltage and can achieve output voltage balancing by using the asymmetrical PWM scheme. A 1.6-kW prototype of the proposed converter was built and tested to verify the performance.

Design of the Circuit for a Power Factor Correction using the Two-Input Current Resonant (2분할 전류유입 공진 회로를 이용한 PFC회로의 설계)

  • Jang, W.S.;Koh, K.H.;Seo, K.Y.;Lee, H.W.;Kwak, D.K.
    • Proceedings of the KIEE Conference
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    • 2001.10a
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    • pp.233-235
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    • 2001
  • On the active filter converter for power factor correction is used inverter for a air-conditioner's power supply to meet IEC standard In the active filter topology for power factor correction, extra switch only control the input current indirectly to satisfied with the IEC standard for reducing the cost and size. In this paper, by dividing the input current into two different modes, the current conduction period can be widened and harmonics can largely be canceled between the two modes. Hence, the harmonics characteristics can be significantly improved, whereby the lower order harmonics, such as the fifth and seventh orders, are much reduced. The results are confirmed by theoretical and experimental implementations.

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