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http://dx.doi.org/10.5207/JIEIE.2004.18.4.041

A Design of PFC Circuit for Reducing the Harmonic in Constant Voltage-fed Electronic Ballast Circuit  

이현우 (경남대학교 전기전자공학부)
이현무 (경남대학교 전기전자공학)
고강훈 (경남대학교 전기전자공학)
고희석 (경남대학교 전기전자공학부)
Publication Information
Journal of the Korean Institute of Illuminating and Electrical Installation Engineers / v.18, no.4, 2004 , pp. 41-48 More about this Journal
Abstract
In this paper, a PFC(Power Factor Correction) electronic ballast with constant voltage-fed is proposed. The proposed PFC electronic ballast is combined of a high-efficiency boost converter and a conventional half bridge inverter. It is proved that the ripple of input-current and the input-current's harmonic of the proposed PFC electronic ballast are reduced using the voltage divider and soft-switching technique. It is demonstrated that simulation results for fluorescent lamp correspond with theoretical analysis.
Keywords
PFC; electronic ballast; soft-Switching technique;
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