• ETRI Journal
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• v.37 no.3
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• pp.523-532
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• 2015

Recently, we have witnessed the gradual miniaturization of electronic devices. In miniaturized devices, flip-chip bonding has become a necessity over other bonding methods. For the electrical connections in miniaturized devices, fine-pitch solder bumping has been widely studied. In this study, high-volume solder-on-pad (HV-SoP) technology was developed using a novel maskless printing method. For the new SoP process, we used a special material called a solder bump maker (SBM). Using an SBM, which consists of resin and solder powder, uniform bumps can easily be made without a mask. To optimize the height of solder bumps, various conditions such as the mask design, oxygen concentration, and processing method are controlled. In this study, a double printing method, which is a modification of a general single printing method, is suggested. The average, maximum, and minimum obtained heights of solder bumps are $28.3{\mu}m$, $31.7{\mu}m$, and $26.3{\mu}m$, respectively. It is expected that the HV-SoP process will reduce the costs for solder bumping and will be used for electrical interconnections in fine-pitch flip-chip bonding.

• Journal of Institute of Control, Robotics and Systems
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• v.15 no.9
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• pp.916-921
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• 2009

The technology to inspect and measure an inner structure of micro parts has become an important tool in the semi-conductor industrial field with the development of automation and precision manufacturing. Especially, the inspection skill on the inside of highly integrated electronic device becomes a key role in detecting defects of a completely assembled product. X-ray inspection technology has been focused as a main method to inspect the inside structure. However, there has been insufficient research done on the customized inspection technology for the flip-chip assembly due to the interior connecting part of flip chip which connects the die and PCB electrically through balls positioned on the die. In this study, therefore, it is implemented to detect shape error of flip chip bonding without damaging chips using an x-ray inspection system. At this time, it is able to monitor the solder bump shape by introducing an edge-extracting algorithm (exponential approximation function) according to the attenuating characteristic and detect shape error compared with CAD data. Additionally, the bonding error of solder bumps is automatically detectable by acquiring numerical size information at the extracted solder bump edges.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.10
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• pp.752-757
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• 2018

This study presents the performance evaluation results of a 77-GHz waveguide slot array antenna that was fabricated by attaching a patterned printed circuit board(PCB) on a metal block. The 77-GHz waveguide was divided into a top plate and a bottom structure. The top plate was fabricated using a patterned PCB that can implement a fine slot at low cost. The top cover was then bonded to the bottom metal structure with a waveguide trough using anisotropic conductive film. For evaluating the antenna performance, a $1{\times}16$ slot array antenna was fabricated using our proposed method and the gain and pattern were measured and compared with the simulation results. Though the measurement results demonstrate a reduction in gain of around 2.3~3.5 dB compared to the simulation results assuming ideal bonding conditions, the pattern hardly changed and the slot antenna with a gain of approximately 17 dBi at 77 GHz can be easily manufactured at a low cost using the proposed method.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.11
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• pp.1228-1238
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• 2012

In this paper, we design, fabricate and measure two kinds of high-frequency packages for K-band CMOS FMCW radar chips using RF via structures. The packages are fabricated with the conventional PCB process and LTCC process. The design centering of the packages is performed at 24 GHz and impedance variation caused by the wire bonding and RF via structure is fully evaluated using 3D electromagnetic simulation. The RF via structure with characteristic impedance of $50{\Omega}$ is used to reduce impedance mismatch loss. Two kinds of test packages with back-to-back connected RF paths are fabricated and measured for the design verification of the PCB-based package and LTCC package. Their measured results show an insertion loss of less than 0.4 dB at 24 GHz and less than 0.5 dB for 20~29 GHz. The measured return loss is less than -13 dB for the PCB-based package and less than -15 dB for the LTCC package in the frequency band, but the return loss of the package itself is predicted to be better than that of the test package by about 5 dB, because the ripples of the back-to-back connection typically degrade the return loss by 5 dB or more.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.32 no.1
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• pp.6-12
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• 2019

Bonding properties of epoxy-containing solder joints were investigated by a high temperature aging test. Specimens were prepared by bonding an R3216 standard chip resistor to an OSP-finished PCB by a reflow process with two basic types of solder (SAC305 & Sn58Bi) pastes and two epoxy-solder (SAC305+epoxy & Sn58Bi+epoxy) pastes. In all epoxy solder joints, an epoxy fillet was formed in the hardened epoxy, lying around the outer edge of the solder joint, between the chip and the Cu pad. In order to analyze the bonding characteristics of solder joints at high temperatures, a high-temperature aging test at $150^{\circ}C$ was carried out for 14 days (336 h). After aging, the intermetallic compound $Cu_6Sn_5$ was found to have formed in the solder joint on the Cu pad, and the shear stress on the conventional solder joint was reduced by a significant amount. The reason that the shear force did not decrease much, even though in epoxy solder, was thatbecause epoxy hardened at the outer edge of the supported solder joints. Using epoxy solder, strong bonding behavior can be ensured due to this resistance to shear force, even in metallurgical changes such as those where intermetallic compounds form at solder joints.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.2
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• pp.63-67
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• 2011

We investigated effects of bonding conditions on the peel strength of rigid printed circuit board (RPCB)/ flexible printed circuit board (FPCB) joints bonded using a thermo-compression bond method, The electrodes on the FPCB were coated with Sn by a dipping process. We confirmed that the bonding temperature and bonding time strongly affected the bonding configuration and strength of the joints. Also, the peel strength is affected by dipping conditions; the optimum dipping condition was found to be temperature of $270^{\circ}C$ and time of 1s. The bonding strength linearly increased with increasing bonding temperature and time until $280^{\circ}C$ and 10s. The fracture energy calculated from the F-x (Forcedisplacement) curve during a peel test was the highest at bonding temperature of $280^{\circ}C$.

• Asia-Pacific Journal of Business Venturing and Entrepreneurship
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• v.7 no.3
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• pp.17-25
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• 2012

Wire bonding process in making semiconductor needs the most precise control and Critical To Quality(CTQ). Thus, it is regarded to be the most essential step in packaging process. In this process, pure gold wire is used to connect the chip and PCB(substrate or lead frame). However, the price of gold has been skyrocketing continuously for a long period of time and is expected to further increase in the near future. This phenomenon situates us in an unfavorable condition amidst the competitive environment. To avoid this situation, many semiconductor material making companies developed new types of wires: Au.Ag wire is one material followed by many others. This study is aimed to optimize the parameter in wire bonding with the use of 6sigma and QFD(Quality Function Deployment). 6sigma process is a good means to not only solve the problem, but to increase productivity. In order to find the key factor, we focused on VOB(Voice of Business) and VOC(Voice of Customer). The main factors from VOB, VOC are called CTQ. However, there were times when these main factors were far from offering us the correct answer, thus making the situation more difficult to handle. This study shows that QFD aids in deciding which of the accurate factors to undertake. Normally QFD is used in designing and developing products. 6sigma process is held more effective when it used with QFD.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.1
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• pp.39-47
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• 2007

It is investigated how KOH and Rthylenediamine(EDA) treatment conditions on Polyimide film surface affect the interfacial fracture energy between electroless plated Ni and Polyimide film by $180^{\circ}$ peel test. Estimated values of interfacial fracture energy were 24.5 g/mm and 33.3 g/mm for the KOH treatment times under 1 and 5 minutes, respectively, while, those were 31.6 g/mm and 22.3 g/mm for EDA treatment times under 1 and 5 minutes, respectively. Interfacial bonding between electroless plated Ni and Polyimide seems to be dominated by chemical bonding effect rather than mechanical interlocking effect. It is found that chemical treatment produces carboxyl and mine functional groups which are closely related the interfacial bonding mechanism. Finally, it is speculated that interfacial fracture energy seems to be controlled by O=C-O bonding near cohesive failure region.

• Journal of the Microelectronics and Packaging Society
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• v.28 no.1
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• pp.47-54
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• 2021

For the bonding of smaller PCB solder bumps of less than 100 microns, an experiment was performed to make up a tin plating solution and find plating conditions in order to produce a bump pattern through tin electroplating, replacing the previous PCB solder bumps process by microballs. After SR patterning, a Cu seed layer was formed, and then, through DFR patterning, a pattern in which Sn can be selectively plated only within the SR pattern was formed on the PCB substrate. The tin plating solution was made based on methanesulfonic acid, and hydroquinone was used as an antioxidant to prevent oxidation of divalent tin ions. Triton X-100 was used as a surfactant, and gelatin was used as a grain refiner. By measuring the electrochemical polarization curve, the characteristics of organic additives in Triton X-100 and gelatin were compared. It was confirmed that the addition of Triton X-100 suppressed hydrogen generation up to -1 V vs. NHE, whereas gelatin inhibited hydrogen generation up to -0.7 V vs. NHE. As the current density increased, there was a general tendency that the grain size became finer, and it was observed that it became finer when gelatin was added.

• Korean Journal of Materials Research
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• v.17 no.3
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• pp.152-159
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• 2007

When the electronics are tested with thermal shock for Pb-free solder joint reliability, there are temperature conditions with use environment but number of cycles for test don't clearly exist. To obtain the long term reliability data, electronic companies have spent the cost and times. Therefore this studies show the test method and number of thermal shock cycles for evaluating the solder joint reliability of electronic components and also research bonding strength variation with formation and growth of intermetallic compounds (IMC). SMD (surface mount device) 3216 chip resistor and 44 pin QFP (quad flat package) was utilized for experiments and each components were soldered with Sn-40Pb and Sn-3.0 Ag-0.5 Cu solder on the FR-4 PCB(printed circuit board) using by reflow soldering process. To reliability evaluation, thermal shock test was conducted between $-40^{\circ}C\;and\;+125^{\circ}C$ for 2,000 cycles, 10 minute dwell time, respectively. Also we analyzed the IMCs of solder joint using by SEM and EDX. To compare with bonding strength, resistor and QFP were tested shear strength and $45^{\circ}$ lead pull strength, respectively. From these results, optimized number of cycles was proposed with variation of bonding strength under thermal shock.