• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.1
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• pp.53-61
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• 2014

In this paper, we present the design, fabrication and measurement of high efficiency GaN HEMT power amplifier using harmonic matching technique. In order to achieve high efficiency, harmonic load-pull simulation is performed, that is, the optimum load impedances are determined at $2^{nd}$ and $3^{rd}$ harmonic frequencies as well as at the fundamental. Then, the output matching circuit is designed based on harmonic load-pull simulation. The measurement of the fabricated power amplifier shows the linear gain of 20 dB and $P_{1dB}$(1 dB gain compression point) of 33.7 dBm at 1.85 GHz. The maximum power added efficiency(PAE) of 80.9 % is achieved at the output power of 38.6 dBm, which belongs to best efficiency performance among the reported high efficiency power amplifiers. For W-CDMA input signal, the power amplifier shows a PAE of 27.8 % at the average output power of 28.4 dBm, where an ACLR (Adjacent Channel Leakage Ratio) is measured to be -38.8 dBc. Digital predistortion using polynomial fitting was implemented to linearize the power amplifiers, which allowed about 6.2 dB improvement of an ACLR performance.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.6
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• pp.584-597
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• 2011

In this paper, low-loss and high-power RF SP6T switch chips are designed, fabricated and measured for GSM/EGSM/DCS/PCS applications using WIN Semiconductors 0.5 ${\mu}m$ pHEMT process. We utilized a combined configuration of series and series-shunt structures for optimized switch performance, and a common transistor structure on a receiver path for reducing chip area. The gate width and the number of stacked transistors are determined using ON/OFF input power level of the transceiver system. To improve the switch performance, feed-forward capacitors, shunt capacitors and parasitic FET inductance elimination due to resonance are actively used. The fabricated chip size is $1.2{\times}1.5\;mm^2$. S-parameter measurement shows an insertion loss of 0.5~1.2 dB and isolation of 28~36 dB. The fabricated SP6T switch chips can handle 4 W input power and suppress second and third harmonics by more than 75 dBc.

• Electrical & Electronic Materials
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• v.12 no.8
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• pp.18-23
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• 1999

InP 소자 기술은 밀리미터파 회로 제작에 지금까지 개발된 기술 중 가장 경쟁력 있는 기술로 InP HEMT와 HBT를 이용하여 100㎓ 이상의 회로가 만들어지고 있다. GaAs 소자 기술에 비해 InP 소자기술은 주파수 특성과 잡음특성, 집적도에 있어서 우수하나 반면에 V-band 이하의 주파수에서 전력특성이 나쁘며, 가격이 비싼 단점이 있다. V-band 이상의 고주파 대역에서 InP 소자기술은 대부분의 면에서 GaAs 소자기술을 능가하여 극초고주파에서 적용가능한 유일한 소자기술이 된다. 본 논문에서는 InP 소자 기술에 대한 기본적인 내용과 응용 예를 소개한다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.2 s.105
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• pp.101-109
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• 2006

A broadband, DC to 40 GHz 5-bit MMIC digital attenuator has been developed. The ultra broadband attenuator has been achieved by adding transmission lines in the conventional Switched-T attenuator and optimizing the transmission line parameters. Momentum simulation was performed in design for accurate performance prediction at high frequencies and Monte Carlo analysis was applied to verify the performance stability against the MMIC process variation. The attenuator has been fabricated with $0.15\;{\mu}m$ GaAs pHEMT process. This attenuator has 1 dB resolution and 23 dB dynamic ranges. High attenuation accuracy has been achieved over all attenuation ranges and 40 GHz bandwidth with the reference state insertion loss of less than 6 dB at 20 GHz. The input and output return losses of the attenuator are better than 14 dB over all attenuation states and frequencies. The measured IIP3 of the attenuator is 33 dBm.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.39-44
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• 2005

A broadband DC to 40 GHz 5-bit MMIC digital attenuator has been developed. The ultra broadband attenuator has been achieved by newly inserted the transmission lines in conventional Switched-T attenuator and the optimization of the transmission line parameters. Momentum was employed in design for an accurate performance prediction at high frequencies and Monte Carlo analysis was applied to verify performance stability against the MMIC process variation. The attenuator has been fabricated with 0.15 $\mu$m GaAs pHEMT process. This attenuator has 1 dB resolution and 23 dB dynamic range. High attenuation accuracy has been achieved over all attenuation range and full 40 GHz bandwidth with the reference state insertion loss of less than 6 dB at 20 GHz. The input and output return losses of the attenuator are better than 14 dB over all attenuation states and frequencies.

• ETRI Journal
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• v.36 no.3
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• pp.510-513
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• 2014

A Q-band pHEMT image-rejection low-noise amplifier (IR-LNA) is presented using inter-stage tunable resonators. The inter-stage L-C resonators can maximize an image rejection by functioning as inter-stage matching circuits at an operating frequency ($F_{OP}$) and short circuits at an image frequency ($F_{IM}$). In addition, it also brings more wideband image rejection than conventional notch filters. Moreover, tunable varactors in L-C resonators not only compensate for the mismatch of an image frequency induced by the process variation or model error but can also change the image frequency according to a required RF frequency. The implemented pHEMT IR-LNA shows 54.3 dB maximum image rejection ratio (IRR). By changing the varactor bias, the image frequency shifts from 27 GHz to 37 GHz with over 40 dB IRR, a 19.1 dB to 17.6 dB peak gain, and 3.2 dB to 4.3 dB noise figure. To the best of the authors' knowledge, it shows the highest IRR and $F_{IM}/F_{OP}$ of the reported millimeter/quasi-millimeter wave IR-LNAs.

• Journal of the Korea Institute of Military Science and Technology
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• v.12 no.4
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• pp.446-451
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• 2009

In this paper, we described the design and test results of a high output power amplifier MMIC developed by using 0.5um power pHEMT processes on a 6-inch GaAs wafer for the X-band T/R module application. In the MMIC design, we have used a simple on-chip gate active bias technology to compensate the threshold-voltage variation of pHEMT during the fabrication process and 16-to-1 power combining method to achieve the output power over 10watt. The fabricated chip has an output power over 12watts and maximum PAE of 32% over the frequency range of fo +/-750MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.5C
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• pp.522-529
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• 2002

MMIC circuits in whole receiver system was fabricated based on GaAs pHEMT technology. And a V-band downconverter module was fabricated by integrating these circuits. The downconverter module consists of a LO drive power amplifier which generates 24dBm output power, a low noise amplifier(LNA) which shows 20 dB small signal gain, an active parallel feedback oscillator which generates 1.6 dBm output power, and a cascode mixer which shows over 6dB conversion gain. The good conversion gain performance of our mixer made no need to attach any IF amplifier which grows conversion gain. Measured results of the complete downconverter show a conversion gain of over 20 dB between 57.5 GHz and 61.7GHz without IF amplifier.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.2 no.2 s.3
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• pp.97-101
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• 2003

A MMIC (monolithic microwave integrated circuit) mixer chip using the Schottky diode of an InGahs/CaAs p-HEMT process has been developed for the receiver down converter of Ku-band. A different approach to the MMIC mixer structure is applied for reducing the chip size by the exchange of ports between If and LO. This MMIC covers with RF (14.0 - 14.5 GHz) and If (12.252 - 12.752 GHz). According to the on-wafer measurement, the miniature (3.3X3.0 m) MMIC mixer demonstrates conversion loss below 9.8 dB, RF-to-IF isolation above 23 dB, LO-to-IF isolation above 38 dB, respectively.

• 전자공학회논문지 IE
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• v.47 no.3
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• pp.47-52
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• 2010

In this paper, a frequency tripler has been designed with 100mW medium-power using P-HEMT. It is designed to obtain 7.2GHz frequency at the output that is an integer multiple of 2.4GHz input frequency by using nonlinear device that produces 3rd harmonic. The frequency tripler is designed by using load-pull simulation. To suppress the 2nd and fundamental, notch filter is used for the frequency tripler. The tripler is designed to obtain about 21dBm output power with 15dBm input, i.e., 6dB conversion gain and the suppression of 20dBc at fundamental, and 30dBc at the second harmonics.