• International journal of advanced smart convergence
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• 제1권1호
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• pp.61-64
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• 2012

The ultraviolet and visible light responsive properties of the amorphous indium gallium zinc oxide thin film transistor have been investigated. Amorphous indium gallium zinc oxide (a-IGZO) thin film transistor operate in the enhancement mode with saturation mobility of $6.99cm^2/Vs$, threshold voltage of 13.5 V, subthreshold slope of 1.58 V/dec and an on/off current ratio of $2.45{\times}10^8$. The transistor was subsequently characterized in respect of visible light and UV illuminations in order to investigate its potential for possible use as a detector. The performance of the transistor is indicates a high-photosensitivity in the off-state with a ratio of photocurrent to dark current of $5.74{\times}10^2$. The obtained results reveal that the amorphous indium gallium zinc oxide thin film transistor can be used to fabricate UV photodetector operating in the 366 nm.

• 전기전자학회논문지
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• 제27권3호
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• pp.303-307
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• 2023

본 논문은 Buried Channel Array Transistor(BCAT) 소자의 Oxide 내부에 Total Ionizing Dose(TID) effects으로 인한 Electron-Hole Pair의 생성이 유도되어, Oxide 계면의 Hole Trap Charge의 증가에 따른 누설전류의 증가와 문턱 전압의 변화를 기존에 제안한 Partial Isolation Buried Channel Array Transistor(Pi-BCAT)구조와 비교 시뮬레이션 하여, Pi-BCAT 소자의 증가한 Oxide 면적과 상관없이 변화한 누설전류와 문턱 전압에서의 특성이 비대칭 도핑 BCAT 구조보다 우수함을 보여 준다.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2010년도 춘계학술대회 논문집
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• pp.707-708
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• 2010

• 한국재료학회:학술대회논문집
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• 한국재료학회 2007년도 추계학술발표대회 및
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• pp.17.1-17.1
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• 2007

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권4호
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• pp.205-210
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• 2003

A 3-Transistor cell CMOS OTP ROM array using standard CMOS antifuse (AF) based on permanent breakdown of MOSFET gate oxide is proposed, fabricated and characterized. The proposed 3-T OTP cell for ROM array is composed of an nMOS AF, a high voltage (HV) blocking nMOS, and cell access transistor, all compatible with standard CMOS technology. The experimental results show that the proposed structure can be a viable technology option as a high density OTP ROM array for modern digital as well as analog circuits.

• Transactions on Electrical and Electronic Materials
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• 제12권1호
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• pp.7-10
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• 2011

High voltage (HV) integrated circuits are viable alternatives to discrete circuits in a wide variety of applications. A HV device generally used in these circuits is a lateral double diffused metal oxide semiconductor (LDMOS) transistor. Attempts to model LDMOS devices are complicated by the existence of the lightly doped drain and by the extension of the poly-silicon and the gate oxide. Several physically based investigations of the bias-dependent drift resistance of HV devices have been conducted, but a complete physical model has not been reported. We propose a new technique to model HV devices using both the BSIM3 SPICE model and a bias dependent resistor model (sub-circuit macro model).

• Transactions on Electrical and Electronic Materials
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• 제12권6호
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• pp.267-270
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• 2011

In the process of inkjet-printed zinc tin oxide thin-film transistor, the effect of metallic interlayer underneath of source and drain electrode was investigated. The reason for the improved electrical properties with thin molybdenum oxide ($MoO_3$) layer was due to the chemically intermixed state of metallic interlayer, aluminum source and drain, and oxide semiconductor together. The atomic configuration of three Mo $3d_3$ and $3d_5$ doublets, three different Al 2p core levels, two Sn $3d_5$, and four different types of oxygen O 1s in the interfaces among those layers was confirmed by X-ray photospectroscopy.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제44회 동계 정기학술대회 초록집
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• pp.582-582
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• 2013

Oxide TFT (thin film transistor) active channel layer에 대한 저온 열처리 공정은 투명하고 flexibility을 기반으로하는 display 산업과 AMOLED (active matrix organic light emitting diode) 분야 등 다양한 분야에서 필요로 하는 기술로서 많은 연구가 이루어지고 있다. 과거 active layer는 ALD (atomic layer deposition), CVD (chemical vapor deposition), pulse laser deposition, radio frequency-dc (RF-dc) magnetron sputtering 등과 같은 고가의 진공 장비를 이용하여 증착 되어져 왔으나 현재에는 진공 장비 없이 spin-coating 후 열처리 하는 저가의 공정이 주로 연구되어 지고 있다. Flexible 기판들은 일반적인 OTFT (oxide thin films Transistor)에 적용되는 열처리 온도로 공정 진행시 열에 의한 기판의 손상이 발생한다. Flexible substrate의 열에 의한 기판 손상을 막기 위해 저온 열처리 공정이 연구되고 있지만 기존 열처리와 비교하여 소자의 특성 저하가 동반 되었다. 본 연구에서는 Si 기판위에 SiO2 (100)를 절연층으로 증착하고 그 위에 IZO (indium zinc oxide) solution을 spin-coating 한뒤 $250^{\circ}C$ 이하의 온도에서 열처리하였다. 저온 공정으로 인하여 소자의 특성 저하가 동반 되었으므로 소자의 저하된 특성 복원하고자 post-treatment로 고가의 진공장비가 필요 없고 roll-to roll system 적용이 수월한 remote-type의 APP (atmospheric pressure plasma) 처리를 하였다. Post-treatment로 APP를 이용하여 $250^{\circ}C$ 이하에서 소자에 적용 가능한 on/off ratio를 얻을 수 있었다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제43회 하계 정기 학술대회 초록집
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• pp.256-256
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• 2012

Oxide semiconductors such as zinc tin oxide (ZTO) or indium gallium zinc oxide (IGZO) have attracted a lot of research interest owing to their high potential for application as thin film transistors (TFTs) [1,2]. However, the instability of oxide TFTs remains as an obstacle to overcome for practical applications to electronic devices. Several studies have reported that the electrical characteristics of ZnO-based transistors are very sensitive to oxygen, hydrogen, and water [3,4,5]. To improve the reliability issue for the amorphous InGaZnO (a-IGZO) thin-film transistor, back channel passivation layer is essential for the long term bias stability. In this study, we investigated the instability of amorphous indium-gallium-zinc-oxide (IGZO) thin film transistors (TFTs) by the back channel contaminations. The effect of back channel contaminations (humidity or oxygen) on oxide transistor is of importance because it might affect the transistor performance. To remove this environmental condition, we performed vacuum seasoning before the deposition of hybrid passivation layer and acquired improved stability. It was found that vacuum seasoning can remove the back channel contamination if a-IGZO film. Therefore, to achieve highly stable oxide TFTs we suggest that adsorbed chemical gas molecules have to be eliminated from the back-channel prior to forming the passivation layers.

• E2M - 전기 전자와 첨단 소재
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• 제10권8호
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• pp.783-793
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• 1997

A VLSI implementation of a self-learning neural network integrated circuits using a linearity synapse transistor is investigated. The thickness dependence of oxide current density stress current transient current and channel current has been measured in oxides with thicknesses between 41 and 112 $\AA$, which have the channel width $\times$ length 10 $\times$1${\mu}{\textrm}{m}$, 10 $\times$ 0.3${\mu}{\textrm}{m}$ respectively. The transient current will affect data retention in synapse transistors and the stress current is used to estimate to fundamental limitations on oxide thicknesses. The synapse transistor has represented the neural states and the manipulation which gaves unipolar weights. The weight value of synapse transistor was caused by the bias conditions. Excitatory state and inhitory state according to weighted values affected the drain source current.