• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.139-145
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• 2014

Control of threshold voltage ($V_T$) by ground-plane (GP) technique for planar tunnel field-effect transistor (TFET) is studied for the first time using TCAD simulation method. Although GP technique appears to be similarly useful for the TFET as for the metal-oxide-semiconductor field-effect transistor (MOSFET), some unique behaviors such as the small controllability under weak ground doping and dependence on the dopant polarity are also observed. For $V_T$-modulation larger than 100 mV, heavy ground doping over $1{\times}10^{20}cm^{-3}$ or back biasing scheme is preferred in case of TFETs. Polarity dependence is explained with a mechanism similar to the punch-through of MOSFETs. In spite of some minor differences, this result shows that both MOSFETs and TFETs can share common $V_T$-control scheme when these devices are co-integrated.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.2
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• pp.164-169
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• 2008

The effects of the antisite related defects on the electronic structure of silica and the gate leakage current have been investigated using first-principles calculations. Energy levels related to the antisite defects in silicon dioxide have been introduced into the bandgap, which are nearly 2.0 eV from the top of the valence band. Combining with the electronic structures calculated from first-principles simulations, tunneling currents through the silica layer with antisite defects have been calculated. The tunneling current calculations show that the hole tunneling currents assisted by the antisite defects will be dominant at low oxide field whereas the electron direct tunneling current will be dominant at high oxide field. With increased thickness of the defect layer, the threshold point where the hole tunneling current assisted by antisite defects in silica is equal to the electron direct tunneling current extends to higher oxide field.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.287-287
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• 2012

최근 투명 산화물 반도체(TOS: Transparent Oxide Semiconductor)중에 비정질 산화물 반도체(amorphous oxide semiconductor)를 이용한 트랜지스터 연구가 활발히 진행되고 있다. 비정질 산화물 반도체는 박막 트렌지스터 소자의 Active Layer으로 사용할 수 있다. 본 연구는 RF magnetron sputtering법으로 유리기판 위에 IGZO박막을 증착하였다. 박막 증착 조건은 초기 압력 $3.0{\times}10^{-6}$ Torr, 증착 압력 20 mTorr, 반응가스 Ar 50 sccm, RF power 30w, 증착 온도는 실온으로 고정하였으며, 공정변수로 증착 시간을 변화시키며 IGZO박막을 증착하였다. IGZO 타겟은 $In_2O_3$, $Ga_2O_3$, ZnO 분말을 각각 1:1:1 mol% 조성비로 혼합하여 소결한 타겟을 사용하였다. XRD 분석결과에 따라서 Bragg's 법칙을 만족하는 피크가 나타나지 않는 비정질 구조임을 확인할 수 있었다. 가시광 영역에서(450~700 nm) 모든 박막은 90% 이상 투과도를 나타내었다. 증착시간이 증가할수록 밴드갭이 감소하는 것을 확인하였다. 증착시간이 5분인 경우 캐리어 농도는 $2.2{\times}10^{19}$ $cm^{-3}$, 이동도는 7.5 $cm^2/V-s$, 비저항은 $3.8{\times}10^{-2}{\Omega}$-cm의 반도체 특성을 나타냈고, 박막 트렌지스터 소자의 Active Layer으로 사용할 수 있다.

• Proceedings of the Materials Research Society of Korea Conference
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• 1996.11a
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• pp.46-46
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• 1996

• Transactions on Electrical and Electronic Materials
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• v.16 no.3
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• pp.139-141
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• 2015

Contact resistance of interface between the channel layers and various S/D electrodes was investigated by transmission line method. Different electrodes such as Ti/Au, a-IZO, and multilayer of a-IGZO/Ag/a-IGZO were compared in terms of contact resistance, using the transmission line model. The a-IGZO TFTs with a-IGZO/Ag/a-IGZO of S/D electrodes showed good performance and low contact resistance due to the homo-junction with channel layer.

• Transactions on Electrical and Electronic Materials
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• v.11 no.4
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• pp.155-165
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• 2010

As a promising candidate to replace the conventional floating gate flash memories, polysilicon-oxide-nitride-oxidesilicon (SONOS)-type nonvolatile semiconductor memories have been investigated widely in the past several years. SONOS-type memories have some advantages over the conventional floating gate flash memories, such as lower operating voltage, excellent endurance and compatibility with standard complementary metal-oxide-semiconductor (CMOS) technology. However, their operating speed and date retention characteristics are still the bottlenecks to limit the applications of SONOS-type memories. Recently, various approaches have been used to make a trade-off between the operating speed and the date retention characteristics. Application of high-k dielectrics to SONOS-type memories is a predominant route. This article provides the state-of-the-art research progress of high-k dielectrics applicable to SONOS-type nonvolatile semiconductor memories. It begins with a short description of working mechanism of SONOS-type memories, and then deals with the materials' requirements of high-k dielectrics used for SONOS-type memories. In the following section, the microstructures of high-k dielectrics used as tunneling layers, charge trapping layers and blocking layers in SONOS-type memories, and their impacts on the memory behaviors are critically reviewed. The improvement of the memory characteristics by using multilayered structures, including multilayered tunneling layer or multilayered charge trapping layer are also discussed. Finally, this review is concluded with our perspectives towards the future researches on the high-k dielectrics applicable to SONOS-type nonvolatile semiconductor memories.

• Proceedings of the Materials Research Society of Korea Conference
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• 1998.08a
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• pp.64.4-64
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• 1998

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.543-544
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• 2008

In the fabrication of inverted top emission organic light emitting diodes (ITOLEDs), the organic layers are damaged by high-energy plasma sputtering process for transparent top anode. In this study, the plasma process induced damages on metal oxide hole injection layers (HILs) including $WO_3$, $MoO_3$, and $V_2O_5$ as buffer layer are examined. With the result of IV characteristic of hole-only devices, we propose that $MoO_3$ and $V_2O_5$ are stable materials against plasma sputtering process.

• Journal of IKEEE
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• v.17 no.4
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• pp.531-536
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• 2013

The impact of UV irradiation process on the AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistor was investigated. Due to the high intensity UV irradiation before the gate dielectric deposition, the conductivity of AlGaN/GaN structure and the drain saturation current of the transistor increased by about 10 %. However, the pinch off characteristics of transistor was severely deformed by the process. By comparing the electrical characteristics of the transistors, it was proposed that the high intensity UV irradiation formed a sub-channel under the two dimensional electron gas of AlGaN/GaN structure even without additional impurity injection.

• Journal of the Semiconductor & Display Technology
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• v.15 no.1
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• pp.52-55
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• 2016

GZO film was prepared on p-type Si wafer and then annealed at various temperatures in an air conditions to research the bonding structures in accordance with the annealing processes. GZO film annealed in an atmosphere showed the various bonding structure depending on annealing temperatures and oxygen gas flow rate during the deposition. The difference of bonding structures of GZO films made by oxygen gas flows between 18 sccm and 22 sccm was so great. The bonding structures of GZO films made by oxygen gas flow of 18 sccm were showed the crystal structure, but that of 22 sccm were showed the amorphous structure in spite of after annealing processes. The bonding structure of GZO as oxide-semiconductor was observed the trend of becoming amorphous structures at the temperature of $200^{\circ}C$. Therefore, the characteristics of oxide semiconductor are needed to research the variation near the annealing at $200^{\circ}C$.