• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.10
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• pp.844-850
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• 2002

Linearly graded profiles on the field area oxide are frequently used in power integrated circuits to reduce the surface electric field when power devices are operated in forward or reverse blocking modes. It is shown here that tapered windows can be made using the difference of etch rates between the bottom and the top layer of TEOS film. Annealed TEOS films are etched at a lower rate than the TEOS film without annealing Process. The fast etching layer results in window walls having slopes in the range of 25$^{\circ}$∼ 80$^{\circ}$ with respect to the wafer surface. Taper etching technique by annealing the TEOS film applies to high voltage LDMOS, which is compatible with CMOS process, due to the minimum changes in both of design rules and thermal budget.

• Transactions on Electrical and Electronic Materials
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• v.16 no.6
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• pp.312-316
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• 2015

Through silicon via (TSV) technology holds the promise of chip-to-chip or chip-to-package interconnections for higher performance with reduced signal delay and power consumption. It includes high aspect ratio silicon etching, insulation liner deposition, and seamless metal filling. The desired etch profile should be straightforward, but high aspect ratio silicon etching is still a challenge. In this paper, we investigate the use of etch hard mask for finer TSVs etching to have clear definition of etched via pattern. Conventionally employed photoresist methods were initially evaluated as reference processes, and oxide and metal hard mask were investigated. We admit that pure metal mask is rarely employed in industry, but the etch result of metal mask support why hard mask are more realistic for finer TSV etching than conventional photoresist and oxide mask.

• Corrosion Science and Technology
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• v.10 no.1
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• pp.37-42
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• 2011

Aluminum was electrochemically etched in acid solution and the surface area was magnified by the formation of etch pits. Etched aluminum was covered with a compact and dense dielectric oxide film by anodization and applied to the aluminum electrolytic capacitor electrode. Capacitance of aluminum electrolytic capacitor is closely related with surface area, which depends on size and number of etch pits. Size of etch pits need to be controlled because inside of the pits can be buried by the formation of dielectric oxide film. In this work, the effect of ultrasound pretreatment on the aluminum etch pit formation and capacitance were investigated. Additionally, the relationship between the second etching effect on pit size and capacitance was studied.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2015.11a
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• pp.244-245
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• 2015

PEALD TiN 금속 전극을 갖는 MOS device에서 SC1 ($NH_4/H_2O_2/H_2O=1:2:5$), SPM ($H_2SO_4/H_2O_2=10:1$), $H_2O_2$ etch chemical을 이용해 TiN 식각 후 oxide 표면 잔류 Ti에 의한 전기적 특성 분석을 진행 하였다. Etch chemical 중 SPM을 이용한 소자의 전기적 특성이 우수하였는데, 이는 잔류Ti atom의 양이 다른 etch chemical을 사용한 것 대비 낮았기 때문이다. 이로 인하여 낮은 leakage current, less frequency dependence의 특성이 관찰되었다. 또한, 후속 열처리를 통해 더욱 우수한 특성이 관찰 되었다. 이러한 공정기술은 single 전극을 갖는 CMOS 형성 시 사용 될 수 있을 것으로 기대된다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.10
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• pp.752-758
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• 2010

The etching characteristics of indium tin oxide (ITO) thin films in an $O_2/BCl_3/Ar$ plasma were investigated. The etch rate of ITO thin films increased with increasing $O_2$ content from 0 to 2 sccm in $BCl_3$/Ar plasma, whereas that of ITO decreased with increasing $O_2$ content from 2 sccm to 6 sccm in $BCl_3$/Ar plasma. The maximum etch rate of 65.9 nm/m in for the ITO thin films was obtained at 2 sccm $O_2$ addition. The etch conditions were the RF power of 500 W, the bias power of 200 W, the process pressure of 15 mTorr, and the substrate temperature of $40^{\circ}C$. The analysis of x-ray photo electron spectroscopy (XPS) was carried out to investigate the chemical reactions between the surfaces of ITO thin films and etch species.

• Journal of the Korean Vacuum Society
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• v.8 no.4A
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• pp.490-495
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• 1999

In 0.18 $\mu \textrm m$ LOGIC device, the etch rate of NMOS polysilicons is different from that of PMOS polysilicons due to the state of polysilicon to manufacture gate line. To control the etch profile, we tested the ratio of $Cl_2$/HBr gas and the total chamber pressure, and also we reduced Back He pressure to get the vertical profile. In the case of manufacturing the gate photoresist line, we used Bottom Anti-Reflective Coating (BARC) to protect refrection of light. As a result we found that $CF_4O_2$ gas is good to etch BARC, because of high selectivity and good photoresist line profile after etching BARC. in the results of the characterization of plasma damage to the antenna effect of gate oxide, NO type thin film(growing gate oxide in 0, ambient followed by an NO anneal) is better than wet type thin film(growing gate oxide in $0_2+H_2$ ambient).

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.5
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• pp.353-360
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• 2012

As semiconductor device technology continuously shrinks, low-open area etch process prevails in front-end etch process, such as contact etch as well as one cylindrical storage (OCS) etch. To eliminate over loaded wafer processing test, it is commonly performed to emply diced small coupons at stage of initiative process development. In nominal etch condition, etch responses of whole wafer test and coupon test may be regarded to provide similar results; however, optical emission spectroscopy (OES) which is frequently utilize to monitor etch chemistry inside the chamber cannot be regarded as the same, especially etch mask is not the same material with wafer chuck. In this experiment, we compared OES data acquired from two cases of etch experiments; one with coupon etch tests mounted on photoresist coated wafer and the other with coupons only on the chuck. We observed different behaviors of OES data from the two sets of experiment, and the analytical results showed that careful investigation should be taken place in OES study, especially in coupon size etch.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07b
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• pp.830-833
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• 2003

This paper describes the fabrication and characteristics of 3C-SiCOI sotctures by SDB and etch-back technology for high-temperature MEMS applications. In this work, insulator layers were formed on a heteroepitaxial 3C-SiC film grown on a Si(001) wafer by thermal wet oxidation and PECVD process, successively. The pre-bonding of two polished PECVD oxide layers made the surface activation in HF and bonded under applied pressure. The wafer bonding characteristics were evaluated by the effect of HF concentration used in the surface treatment on the roughness of the oxide and pre-bonding strength. Hydrophilic character of the oxidized 3C-SiC film surface was investigated by ATR-FTIR. The strength of the bond was measured by tensile strengthmeter. The bonded interface was also analyzed by SEM. The properties of fabricated 3C-SiCOI structures using etch-back technology in TMAH solution were analyzed by XRD and SEM. These results indicate that the 3C-SiCOI structure will offers significant advantages in the high-temperature MEMS applications.

• Journal of the Korean Ceramic Society
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• v.53 no.6
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• pp.700-706
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• 2016

Etch rate, surface roughness and microstructure as plasma resistance were evaluated for six kinds of oxide glass with different compositions. Borosilicate glass (BS) was found to be etched at the highest etch rate and zinc aluminum phosphate glass (ZAP) showed a relatively lower etch rate than borosilicate. On the other hand, the etching rate of calcium aluminosilicate glass (CAS) was measured to be similar to that of sintered alumina while yttrium aluminosilicate glass (YAS) showed the lowest etch rate. Such different etch rates by mixture plasma as a function of glass compositions was dependent on whether or not fluoride compounds were formed on glass and sublimated in high vacuum. Especially, in view that $CaF_2$ and $YF_3$ with high sublimation points were formed on the surface of CAS and YAS glasses, both CAS and YAS glasses were considered to be a good candidate for protective coating materials on the damaged polycrystalline ceramics parts in semi-conductor and display processes.

• Korean Chemical Engineering Research
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• v.47 no.1
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• pp.79-83
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• 2009

In this study, the characteristics of amorphous silicon etching for the formation of gate electrodes have been evaluated at the variation of several process parameters. When total flow rates composed of $Cl_2/HBr/O_2$ gas mixtures increased, the etch rate of amorphous silicon layer increased, but critical dimension (CD) bias was not notably changed regardless of total flow rate. As the amount of HBr in the mixture gas became larger, amorphous silicon etch rate was reduced by the low reactivity of Br species. In the case of increasing oxygen flow rate, etch selectivity was increased due to the reduction of oxide etch rate, enhancing the stability of silicon gate etching process. However, gate electrodes became more sloped according to the increase of oxygen flow rate. Higher source power induced the increase of amorphous silicon etch rate and CD bias, and higher bias power had a tendency to increase the etch rate of amorphous silicon and oxide.