• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.1105-1106
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• 2008

Staggered type self-aligned transparent-oxide-semiconductor transistors with indium-zinc-oxide as a semiconductor have studied. In this device fabrication, successive sputtering of oxide semiconductor and insulator without breaking of vacuum and without exposing in air, humidity and oxygen can be realized because oxide semiconductor is transparent. As a result of fabrication, transistor characteristics with mobility of $30cm^2/Vs$ and on-off ratio of $10^5$ could be obtained for the newly developed self-alignment device structure.

• Transactions on Electrical and Electronic Materials
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• v.12 no.1
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• pp.7-10
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• 2011

High voltage (HV) integrated circuits are viable alternatives to discrete circuits in a wide variety of applications. A HV device generally used in these circuits is a lateral double diffused metal oxide semiconductor (LDMOS) transistor. Attempts to model LDMOS devices are complicated by the existence of the lightly doped drain and by the extension of the poly-silicon and the gate oxide. Several physically based investigations of the bias-dependent drift resistance of HV devices have been conducted, but a complete physical model has not been reported. We propose a new technique to model HV devices using both the BSIM3 SPICE model and a bias dependent resistor model (sub-circuit macro model).

• Transactions on Electrical and Electronic Materials
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• v.12 no.1
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• pp.16-19
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• 2011

The oxide-nitride-oxide (ONO) deposition process was added to the beginning of a 0.25 ${\mu}m$ embedded polysiliconoxide-nitride-oxide-silicon (SONOS) process before all of the logic well implantation processes in order to maintain the characteristics of basic CMOS(complementary metal-oxide semiconductor) logic technology. The system subsequently suffered severe ONO rupture failure. The damage was caused by the ONO implantation and was responsible for the ONO rupture failure in the embedded SONOS process. Furthermore, based on the experimental results as well as an implanted ion's energy loss model, processes primarily producing permanent displacement damages responsible for the ONO rupture failure were investigated for the embedded SONOS process.

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.05a
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• pp.16.1-16.1
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• 2009

We have fabricated solution processed oxide semiconductor active layer for thin film transistors (TFTs). The oxide semiconductor layers were prepared by ink-jet printing the sol-gel precursor solution based on doped-ZnO. Inorganic ZnO-based thin films have drawn significant attention as an active channel layer for TFTs applications alternative to conventional Si-based materials and organic semiconducting materials, due to their wide energy band gap, optical transparency, high mobility, and better stability. However, in spite of such excellent device performances, the fabrication methods of ZnO related oxide active layer involve high cost vacuum processes such as sputtering and pulsed laser deposition. Herein we introduced the ink-jet printing technology to prepare the active layers of oxide semiconductor. Stable sol-gel precursor solutions were obtained by controlling the composition of precursor as well as solvents and stabilizers, and their influences on electrical performance of the transistors were demonstrated by measuring electrical parameters such as off-current, on-current, mobility, and threshold voltage. Microstructure and thermal behavior of the doped ZnO films were investigated by SEM, XRD, and TG/DTA. Furthermore, we studied the influence of the ink-jet printing conditions such as substrate temperature and surface treatment on the microstructure of the ink-jet printed active layers and electrical performance. The mobility value of the device with optimized condition was about 0.1-1.0 $cm^2/Vs$ and the on/off current ratio was about $10^6$. Our investigations demonstrate the feasibility of the ink-jet printed oxide TFTs toward successful application to cost-effective and mass-producible displays.

• Transactions on Electrical and Electronic Materials
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• v.16 no.5
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• pp.254-259
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• 2015

This paper reports the optimized mixed-signal performance of a high-voltage (HV) laterally double-diffused metaloxide-semiconductor (LDMOS) field-effect transistor (FET) with a dual gate oxide (DGOX). The fabricated device is based on the split-gate FET concept. In addition, the gate oxide on the source-side channel is thicker than that on the drain-side channel. The experiment results showed that the electrical characteristics are strongly dependent on the source-side channel length with a thick gate oxide. The digital and analog performances according to the source-side channel length of the DGOX LDMOS device were examined for circuit applications. The HV DGOX device with various source-side channel lengths showed reduced by maximum 37% on-resistance (R_ON) and 50% drain conductance (g_ds). Therefore, the optimized mixed-signal performance of the HV DGOX device can be obtained when the source-side channel length with a thick gate oxide is shorter than half of the channel length.

• Journal of the Semiconductor & Display Technology
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• v.22 no.1
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• pp.28-32
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• 2023

Recently, the use of stable lithium nanostructures as substrates and electrodes for secondary batteries can be a fundamental alternative to the development of next-generation system semiconductor devices. However, lithium structures pose safety concerns by severely limiting battery life due to the growth of Li dendrites during rapid charge/discharge cycles. Also, enabling long cyclability of high-voltage oxide cathodes is a persistent challenge for all-solid-state batteries, largely because of their poor interfacial stabilities against oxide solid electrolytes. For the development of next-generation system semiconductor devices, solid electrolyte nanostructures, which are used in high-density micro-energy storage devices and avoid the instability of liquid electrolytes, can be promising alternatives for next-generation batteries. Nevertheless, poor lithium ion conductivity and structural defects at room temperature have been pointed out as limitations. In this study, a low-dimensional Graphene Oxide (GO) structure was applied to demonstrate stable operation characteristics based on Li+ ion conductivity and excellent electrochemical performance. The low-dimensional structure of GO-based solid electrolytes can provide an important strategy for stable scalable solid-state power system semiconductor applications at room temperature. The device using uncoated bare NCA delivers a low capacity of 89 mA h g-1, while the cell using GO-coated NCA delivers a high capacity of 158 mA h g−1 and a low polarization. A full Li GO-based device was fabricated to demonstrate the practicality of the modified Li structure using the Li-GO heterointerface. This study promises that the lowdimensional structure of Li-GO can be an effective approach for the stabilization of solid-state power system semiconductor architectures.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.390-392
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• 2013

The research was observed the characteristic of ZnO based oxide semiconductors for the transparent conducting display. The optical-physical properties of ZnO based oxide semiconductors) grown on p-Si wafer were presented. ZnO based oxide semiconductors was prepared by the RF magnetron sputtering system. The characteristic of ZnO based oxide semiconductorswas strongly influenced by the amount of localized electron state by the defects. The PL spectra moved to long wave number with increasing the defects in the film. The mobility of a-IGZO film was increased with increasing the oxygen gas flow rate. The resistivity of ZnO based oxide semiconductors was also related to the mobility of ZnO based oxide semiconductors, and the mobility increased at the sample with low resistivity. The electric characteristic of a-IGZO TFTs showed that it is an n-type semiconductor.

• Proceedings of the Materials Research Society of Korea Conference
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• 2007.11a
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• pp.17.1-17.1
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• 2007

• Journal of the Semiconductor & Display Technology
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• v.22 no.1
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• pp.78-82
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• 2023

Metal oxide semiconductor (MOS) adapting spray-pyrolysis deposition technique has drawn large attention based on their high quality of intrinsic and electrical properties in addition to simple and low-cost processibility. To fully utilize the merits of MOS field-effect transistors (FETs) , transparency, it is important to understand the instability behaviors of FETs under illumination. Here, we studied the photo-induced properties of nc-ZnO/ZnO field-effect transistors (FETs) based on spray-pyrolysis under illumination which incorporating ZnO nanocrystalline nanoparticles into typical ZnO precursor. Our experiments reveal that nc-ZnO in active layer suppressed the light instabilities of FETs.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.120-124
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• 2004

본 연구는 Diluted Ceria 입자를 사용한 $SiO_2$(Oxide) CMP 현상에 대한 내용이다. Ceria Slurry의 경우 Silica Slurry와 비교하였을 때 Oxide Wafer 표면과 축합 화학반응을 일으키며 Chemistry Dominant한 CMP Mechanism을 따르고, Wafer Center Removal Rate(RR) Fast 의 특성을 가진다. Ceria Slurry의 문제점인 연마 불균일도를 해결하기 위해 Tribological System을 이용하였다. CMP Tribology는 Pad-Slurry 유막-Wafer의 System을 가지며 윤활막에 작용하는 마찰계수(COF)가 주요 인자이다. Tribology에 적용되는 Stribeck Curve를 통해 Slurry 윤활막의 두께(h) 정도를 예상할 수 있으며, 이 윤활막의 두께를 조절함으로써 Uniformity 향상이 가능하다. 이 Ceria Slurry CMP의 연마 불균일도를 향상시킬 수 있는 방법으로 pH 조절 및 점도 증가가 있다. Ceria 입자 CMP는 분산액의 pH 변화에 강한 작용을 받게 되며 PH5 근방에서 최적화된 Uniformity가 가능하다. 점도를 증가시키는 경우 유막 h가 증가하게 되어 Ceria Slurry의 유동이 균일 분포 상태에 가까워지며 Wafer Uniformity 향상이 가능하다.