• 한국전기전자재료학회논문지
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• 제13권10호
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• pp.822-827
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• 2000

The Si-SiO$_2$interface trap and nitride bulk trap distribution of SONOSFET(polysilicon-oxide-nitride-oxide-semiconductor field effect transistor) NVSM (nonvolatile semiconductor memory) cell is investigated by single junction charge pumping method. The device was fabricated by 0.35㎛ standard logic fabrication process including the ONO stack dielectrics. The thickness of ONO dielectricis are 24$\AA$ for tunnel oxide, 74 $\AA$ for nitride and 25 $\AA$ for blocking oxide, respectively. By the use of single junction charge pumping method, the lateral profiles of both interface and memory traps can be calculated directly from experimental charge pumping results without complex numerical simulation. The interface traps were almost uniformly distributed over the whole channel region and its maximum value was 7.97$\times$10$\^$10/㎠. The memory traps were uniformly distributed in the nitride layer and its maximum value was 1.04$\times$10$\^$19/㎤. The degradation characteristics of SONOSFET with write/erase cycling also were investigated.

• 반도체디스플레이기술학회지
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• 제7권1호
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• pp.29-34
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• 2008

In this paper, the DE(double erosion) cathode for the reactive magnetron sputtering system is developed for high deposition rate and high target utilization efficiency. The utilization efficiency of the developed DE cathode is 22% higher than that of normal SE(single erosion) cathode. Sputtering process for the nickel oxide thin films with the DE cathode is performed under the following conditions; power with $1kW{\sim}3kW$, pressure with 4mtorr and 8mtorr, oxygen flow ratio with $0%{\sim}80%$. As a result, the hysteresis phenomenon of discharge voltage in 4mtorr is lower than that in 8mtorr and the hysteresis phenomenon of discharge voltage is getting lower as the applied power is getting higher. The structure of cross section and surface roughness of the thin films are observed by FE-SEM and AFM. The structure of cross section of the thin films is columnar and the average surface roughness under oxygen flow ratio of 0%, 52.5% and 65.0% are $2.08{\AA}$, $2.20{\AA}$ and $0.854{\AA}$, respectively.

• 반도체디스플레이기술학회지
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• 제17권2호
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• pp.57-60
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• 2018

Recently, Thin-film transistors (TFTs) are fundamental building blocks for state-of-the-art microelectronics, such as flat-panel displays and system-on-glass. Zinc oxide thin films have the advantage that they can grow at low temperature and can obtain high charge movility. Also the zinc oxide thin film can be used to control the resistance according to the oxygen content, so it is very easy to obtain the desired physical properties. In this paper, we fabricated a zinc oxide thin film on a polished copper substrate through a solution process, then improved the crystallinity through a geat treatment porcess, and studied to transfer it on a flexible substrate after the heat treatment was completed.

• 반도체디스플레이기술학회지
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• 제17권4호
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• pp.32-36
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• 2018

For various oxygen($O_2$) to argon(Ar) gas ratio, aluminum-doped zinc oxide(AZO) films were deposited for 3 min at different duty ratio by changing reverse pulse times. As the duty ratio increased, the thickness of the AZO film decreased and the sheet resistance increased. It can be concluded that When sputtering AZO Thin film, oxygen interfered with sputtering. When the reverse time was increased, the thickness of AZO was proportional to the real sputtering time and decreased. From the optical transmittance and sheet resistance, it was possible to obtain a higher figure of merits of AZO at a lower reverse pulse time. Even at the short reversed pulse time, it can be concluded that the accumulated charges on the AZO target are completely cleared. At a lower reverse pulse time, pulsed-DC sputtering of AZO is expected to be used instead of DC sputtering in the deposition of transparent conductive oxide(TCO) films without any degradation in thickness and structural/electrical characteristics.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권2호
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• pp.106-113
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• 2006

Electrical properties of $Si_{0.88}Ge_{0.12}(C)$ p-MOSFETs have been exploited in an effort to investigate $Si_{0.88}Ge_{0.12}(C)$ channel structures designed especially to suppress diffusion of dopants during epitaxial growth and subsequent fabrication processes. The incorporation of 0.1 percent of carbon in $Si_{0.88}Ge_{0.12}$ channel layer could accomodate stress due to lattice mismatch and adjust bandgap energy slightly, but resulted in deteriorated current-voltage properties in a broad range of operation conditions with depressed gain, high subthreshold current level and many weak breakdown electric field in gateoxide. $Si_{0.88}Ge_{0.12}(C)$ channel structures with boron delta-doping represented increased conductance and feasible use of modulation doped device of $Si_{0.88}Ge_{0.12}(C)$ heterostructures.

• 인포메이션 디스플레이
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• 제9권1호
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• pp.9-15
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• 2008

• 한국산학기술학회논문지
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• 제10권7호
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• pp.1489-1496
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• 2009

비정질 인듐-갈륨-아연 산화물 박막트랜지스터를 모델링 하여서, 능동층의 구조, 두께, 평형상태의 전자밀도에 대응하는 박막트랜지스터의 특성을 연구하였다. 단일 능동층 박막트랜지스터의 경우, 능동층이 얇을 때 높은 전계효과이동도를 보였다. 문턱전압의 절대값은 능동층의 두께가 20 nm일 때 최저치를 보였으며, 문턱전압이하 기울기는 두께에 대한 의존성을 보이지 않았다. 복층구조 능동층의 경우, 하부의 능동층이 높은 평형상태 전자밀도를 가질 때보다 우수한 스위칭 특성을 보였다. 이 경우에도 능동층의 두께가 얇을 때에 높은 전계효과 이동도를 보였다. 높은 평형상태 전자밀도의 능동층의 두께를 증가시키면 문턱전압은 음의 방향으로 이동하였다. 문턱전압이하 기울기는 능동층의 구조에 대하여 특별한 의존성을 보이지 않았다. 이상과 같은 데이터는 산화물반도체 박막트랜지스터 능동층의 구조, 두께, 도핑비율을 최적화함에 효과적으로 사용될 것으로 기대된다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1989년도 하계종합학술대회 논문집
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• pp.377-379
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• 1989

Very thin gate oxide(100-300A) MOS capacitor has been fabricated. The effect of series resistance must be calculated and the exact metal-semiconductor work function difference should be obtained to get the fixed oxide charge density exisiting in oxide. Dilute oxidation make sagy to control oxide thickness and reduce fixed oxide charge density. In case of dilute oxidation, fixed oxide charge density depends on oxidation time. If oxide is very thin, the annealing effect is ignored.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권2호
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• pp.167-173
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• 2017

In this paper, the characterization of the vertical position of trapped charges in the charge-trap flash (CTF) memory is performed in the novel CTF memory cell with gate-all-around structure using technology computer-aided design (TCAD) simulation. In the CTF memories, injected charges are not stored in the conductive poly-crystalline silicon layer in the trapping layer such as silicon nitride. Thus, a reliable technique for exactly locating the trapped charges is required for making up an accurate macro-models for CTF memory cells. When a programming operation is performed initially, the injected charges are trapped near the interface between tunneling oxide and trapping nitride layers. However, as the program voltage gets higher and a larger threshold voltage shift is resulted, additional charges are trapped near the blocking oxide interface. Intrinsic properties of nitride including trap density and effective capture cross-sectional area substantially affect the position of charge centroid. By exactly locating the charge centroid from the charge distribution in programmed cells under various operation conditions, the relation between charge centroid and program operation condition is closely investigated.

• 한국전기전자재료학회논문지
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• 제35권5호
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• pp.504-508
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• 2022

Single crystal gallium oxide (Ga₂O₃) has been an emerging material for power semiconductor applications. However, the defect distribution of Ga₂O₃ substrates needs to be carefully characterized to improve crystal quality during crystal growth. We analyzed the type and the distribution of defects on commercial (-201) Ga₂O₃ substrates to get a basic standard prior to growing Ga₂O₃ crystals. Etch pit technique was employed to expose the type of defects on the Ga₂O₃ substrates. Synchrotron white beam X-ray topography was also utilized to observe the defect distribution by a nondestructive manner. We expect that the observation of defect distribution with three-dimensional geometry will also be useful for other crystal planes of Ga₂O₃ single crystals.