• EDISON SW 활용 경진대회 논문집
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• 제5회(2016년)
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• pp.362-364
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• 2016

본 논문에서는 MOS(Metal Oxide Semiconductor) Capacitor의 산화막내에 다양한 원인에 의해 존재하는 비이상적인 전하들 중 Fixed Oxide Charge가 소자의 문턱전압에 어떤 영향을 주는지 분석했다. 분석한 결과 n+ polysilicon Gate를 가지고, 산화막인 $SiO_2$의 두께가 3nm이고, 도핑농도가 $10^{18}cm^{-2}$인 P형 실리콘 기판으로 이루어진 MOS Capacitor에서 Fixed Oxide Charge Density가 $C/cm^2$ 이상일 때 문턱전압을 0.01V 이상 감소시키고 $C/cm^2$ 이하일 때 문턱전압을 0.01V 이상 증가시켰다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
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• pp.86.1-86.1
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• 2015

As the feature size of Si-based semiconductor shrinks to nanometer scale, we are facing to the problems such as short channel effect and leakage current. One of the solutions to cope with those issues is to bring III-V compound semiconductors to the semiconductor structures, because III-V compound semiconductors have much higher carrier mobility than Si. However, introduction of III-V semiconductors to the current Si-based manufacturing process requires great challenge in the development of process integration, since they exhibit totally different physical and chemical properties from Si. For example, epitaxial growth, surface preparation and wet etching of III-V semiconductors have to be optimized for production. In addition, oxidation mechanisms of III-V semiconductors should be elucidated and re-growth of native oxide should be controlled. In this study, surface preparation methods of various III-V compound semiconductors such as GaAs, InAs, and GaSb are introduced in terms of i) how their surfaces are modified after different chemical treatments, ii) how they will be re-oxidized after chemical treatments, and iii) is there any effect of surface orientation on the surface preparation and re-growth of oxide. Surface termination and behaviors on those semiconductors were observed by MIR-FTIR, XPS, ellipsometer, and contact angle measurements. In addition, photoresist stripping process on III-V semiconductor is also studied, because there is a chance that a conventional photoresist stripping process can attack III-V semiconductor surfaces. Based on the Hansen theory various organic solvents such as 1-methyl-2-pyrrolydone, dimethyl sulfoxide, benzyl alcohol, and propylene carbonate, were selected to remove photoresists with and without ion implantation. Although SPM and DIO3 caused etching and/or surface roughening of III-V semiconductor surface, organic solvents could remove I-line photoresist without attack of III-V semiconductor surface. The behavior of photoresist removal depends on the solvent temperature and ion implantation dose.

• Transactions on Electrical and Electronic Materials
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• 제9권1호
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• pp.6-11
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• 2008

In this study, we investigated effects of hydrogen annealing (HA) and plasma nitridation (PN) applied in order to improve $Si/SiO_2$ interface characteristics of TiN metal gate. In result, HA and PN showed a positive effect decreasing number of interface state $(N_{it})$ respectively. After FN stress for verifying reliability, however, we identified rapid increase of $N_{it}$ for TiN gate with HA, which is attributed to hydrogen related to a change of $Si/SiO_2$ interface characteristic. In contrast to HA, PN showed an improved Nit and gate oxide leakage characteristic due to several possible effects, such as blocking of Chlorine (Cl) diffusion and prevention of thermal reaction between TiN and $SiO_2$.

• 한국전기전자재료학회논문지
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• 제25권9호
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• pp.671-676
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• 2012

In this paper, TCAD assessment of 30-V class n-channel EDMOS (extended drain metal-oxide-semiconductor) transistors with DWFG (dual work function gate) structure are described. Gate of the DWFG EDMOS transistor is composed of both p- and n-type doped region on source and drain side. Additionally, lengths of p- and n-type doped gate region are varied while keeping physical channel length. Two-dimensional device structures are generated trough TSUPREM-4 and their electrical characteristics are investigated with MEDICI. The DWFG EDMOS transistor shows improved electrical characteristics than conventional device - i.e. higher transconductance ($g_m$), better drain output current ($I_{ON}$), reduced specific on-resistances ($R_{ON}$) and higher breakdown characteristics ($BV_{DSS}$).

• 공업화학
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• 제24권1호
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• pp.1-9
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• 2013

의료의 패러다임이 질병 치료에서 질변 예방 및 조기 진단으로 변화하면서 미량의 생분자를 측정할 수 있는 기술에 대한 수요가 증가하고 있다. 미량의 생분자를 측정할 수 있는 다양한 기술이 존재하는데 여기서는 성숙된 반도체 기술을 이용한 바이오센서에 대해 언급하고자 한다. 이의 이해를 돕기 위해 반도체의 기본 소자인 MOSFET (Metal-oxide-semiconductor field-effect transistor)의 구조와 원리를 소개하고, 이를 응용한 ISFET (Ion sensitive FET), BioFET (Biologically modified FET), Nanowire FET, 그리고 IFET (Ionic FET)에 대한 소개와 이의 생명공학에 대한 응용에 대해 논하고자 한다.

• Transactions on Electrical and Electronic Materials
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• 제11권1호
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• pp.15-19
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• 2010

In this paper, we discuss design considerations for an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) with a lateral asymmetric channel (LAC) doping profile. We employed a $0.35\;{\mu}m$ standard complementary MOSFET process for fabrication of the devices. The gates to the LAC doping overlap lengths were 0.5, 1.0, and $1.5\;{\mu}m$. The drain current ($I_{ON}$), transconductance ($g_m$), substrate current ($i_{SUB}$), drain to source leakage current ($i_{OFF}$), and channel-hot-electron (CHE) reliability characteristics were taken into account for optimum device design. The LAC devices with shorter overlap lengths demonstrated improved $I_{ON}$ and $g_m$ characteristics. On the other hand, the LAC devices with longer overlap lengths demonstrated improved CHE degradation and $I_{OFF}$ characteristics.

• 반도체디스플레이기술학회지
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• 제22권4호
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• pp.53-58
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• 2023

The storage capacity of 3D-NAND flash memory has been enhanced by the multi-layer dielectrics. The deposition process has become more challenging due to the tight process margin and the demand for accurate process control. To reduce product costs and ensure successful processes, process diagnosis techniques incorporating artificial intelligence (AI) have been adopted in semiconductor manufacturing. Recently there is a growing interest in process diagnosis, and numerous studies have been conducted in this field. For higher model accuracy, various process and sensor data are required, such as optical emission spectroscopy (OES), quadrupole mass spectrometer (QMS), and equipment control state. Among them, OES is usually used for plasma diagnostic. However, OES data can be distorted by viewport contamination, leading to misunderstandings in plasma diagnosis. This issue is particularly emphasized in multi-dielectric deposition processes, such as oxide and nitride (ON) stack. Thus, it is crucial to understand the potential misunderstandings related to OES data distortion due to viewport contamination. This paper explores the potential for misunderstanding OES data due to data distortion in the ON stack process. It suggests the possibility of excessively evaluating process drift through comparisons with a QMS. This understanding can be utilized to develop diagnostic models and identify the effects of viewport contamination in ON stack processes.

• 한국결정성장학회지
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• 제24권3호
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• pp.106-110
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• 2014

Atomic layer deposition(ALD)을 이용하여 $Al_2O_3$ 박막을 형성하고 이에 대한 패시베이션 특성에 대한 연구를 수행하였다. ALD로 증착된 $Al_2O_3$ 박막은 $400^{\circ}C$ 5분간 후속 열처리 공정 후에도 $Al_2O_3$ - 실리콘 계면 반응 없이 비정질 상태를 유지할 만큼 구조적으로 안정한 특성을 나타내었다. 후속 열처리 후 $Al_2O_3$ 박막의 패시베이션 특성이 향상되었으며, 이는 field effective 패시베이션과 화학적 패시베이션 효과가 동시에 상승에 기인하는 것으로 판단된다. $Al_2O_3$ 박막의 음고정 전하를 정량적으로 평가하기 위해서 후속 열처리 공정을 거친 $Al_2O_3$ 박막을 이용하여 metal-oxide-semiconductor(MOS) 소자를 제작하고 capacitance-voltage(C-V) 분석을 수행하였다. C-V 결과로부터 추출된 flatband voltage($V_{FB}$)와 equivalent oxide thickness(EOT)의 관계식을 통하여 $Al_2O_3$ 박막의 고정음전하는 $2.5{\times}10^{12}cm^{-2}$로 계산되었으며, 이는 본 연구에서 제시된 $Al_2O_3$ 박막 공정이 N-type 실리콘 태양전지의 패시베이션 공정에 응용 가능하다는 것을 의미한다.

• 한국재료학회지
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• 제1권4호
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• pp.229-235
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• 1991

$Ta_2O_5$ 박막은 실리콘산화막, 실리콘질화막 박막에 비해 유전율은 높으나 누설전류밀도가 높고, 절연파괴강도가 낮아 DRAM의 커패시터용 재료로서 실용화가 되지 못하고 있다. 본 연구에서는 LPCVD법으로 형성시킨 $300{\AA}$ 두께의 $Ta_2O_5$ 유전체박막에 대해 후속열처리 또는 전극재료를 변화시켜 열악한 전기적 특성의 원인을 규명하고자 하였다. 그 결과 다결정 실리콘 전극의 경우 성막상태의 $Ta_2O_5$ 박막은 전극에 의한 환원반응에 의해 전기적 특성이 열화됨을 알 수 있었고, 이를 TiN 전극의 사용으로 억제시킬 수 있었다. 다결정 실리콘 전극의 경우 성막상태의 $Ta_2O_5$ 유전체는 누설정류밀도가 $10^{-1}A/cm^2$, 절연파괴강도가 1.5MV/cm 정도였으며, $800^{\circ}C$에서 $O_2$열처리를 하면 전기적 특성은 개선되나, 유전율이 낮아진다 TiN 전극을 채용할 경우 누설전류밀도 $10^{-6}~10^{-7}A/cm^2$, 절연파괴강도 7~12MV/cm 로 ONO(Oxide-Nitride-Oxide) 박막과 비슷한 $Ta_2O_5$ 고유전막을 얻을 수 있었다.

• E2M - 전기 전자와 첨단 소재
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• 제4권2호
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• pp.159-174
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• 1991

이중주입효과에 의한 고내압 반도체 스위칭소자의 설계 제작에 촛점을 맞추어 Injection Gate구조와 MOS Gate 구조로 시료소자를 제작해 그 특성을 검토하고 Electrical Switching 및 Oxide막에서의 Breakdown현상에 의한 문제점을 해결해 보고자 Optical Gate구조를 제안하여 이 optically Gated Semiconductor Switching 소자의 동작특성을 연구하고 Injection Gate 구조를 제안하여 이 optically Gated Semiconductor Switching 소자의 동작특성을 연구하고 Injection Gate 및 MOS Gate 구조(Planar type, V-Groove type, Injection Gate mode, Optical Gate mode)로 설계제작된 소자와 특성을 비교 분석하였다.