• ETRI Journal
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• 제17권4호
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• pp.1-12
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• 1996

A novel body-tied silicon-on-insulator(SOI) n-channel metal-oxide-semiconductor field-effect transistor with grounded body electrode named GBSOI nMOSFET has been developed by wafer bonding and etch-back technology. It has no floating body effect such as kink phenomena on the drain current curves, single-transistor latch and drain current overshoot inherent in a normal SOI device with floating body. We have characterized the interface trap density, kink phenomena on the drain current ($I_{DS}-V_{DS}$) curves, substrate resistance effect on the $I_{DS}-V_{DS}$ curves, subthreshold current characteristics and single transistor latch of these transistors. We have confirmed that the GBSOI structure is suitable for high-speed and low-voltage VLSI circuits.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권6호
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• pp.867-872
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• 2016

We have investigated the channel mobility of AlGaN/GaN-on-Si recessed-metal-oxide-semiconductor-heterojunction field-effect transistors (recessed-MOS-HFET) with $SiO_2$ gate oxide. Both field-effect mobility and effective mobility for the recessed-MOS channel region were extracted as a function of the effective transverse electric field. The maximum field effect mobility was $380cm^2/V{\cdot}s$ near the threshold voltage. The effective channel mobility at the on-state bias condition was $115cm^2/V{\cdot}s$ at which the effective transverse electric field was 340 kV/cm. The influence of the recessed-MOS region on the overall channel mobility of AlGaN/GaN recessed-MOS-HFETs was also investigated.

• Transactions on Electrical and Electronic Materials
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• 제18권5호
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• pp.250-252
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• 2017

High-performance full swing logic inverters were fabricated using amorphous 1 wt% Si doped indium-zinc-oxide (a-SIZO) thin films with different channel layer thicknesses. In the inverter configuration, the threshold voltage was adjusted by varying the thickness of the channel layer. The depletion mode (D-mode) device used a TFT with a channel layer thickness of 60 nm as it exhibited the most negative threshold voltage (-1.67 V). Inverters using enhancement mode (E-mode) devices were fabricated using TFTs with channel layer thicknesses of 20 or 40 nm with excellent subthreshold slope (S.S). Both the inverters exhibited high voltage gain values of 30.74 and 28.56, respectively at $V_{DD}=15V$. It was confirmed that the voltage gain can be improved by increasing the S.S value.

• 한국컴퓨터산업교육학회:학술대회논문집
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• 한국컴퓨터산업교육학회 2003년도 제4회 종합학술대회 논문집
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• pp.67-70
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• 2003

In this paper, propose a new structure of MOFET(Metal-Oxide-Semiconductor Field Effect Transistor) which is widely application for semiconductor technologies. Eleminate the latch-up effect caused by closed devices when conpose a electronic circuit using proposed devices. In this device have a completely isolation structure, and advantage of leakage current elimination. Each independent devices are isolated by trench-well and oxide layer of SOI substrate. Using trench gate and self aligned techniques reduces parasitic capacitance between gate and source, drain. In this paper, we proposed the new structure of SOI MOSFET which has completely isolation and contains trench gate electrodes and SOI wafers. It is simulated by MEDICI that is device simulator.

• 한국전기전자재료학회논문지
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• 제25권8호
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• pp.580-583
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• 2012

The dependency of processing pressure on the electrical performances in amorphous silicon-zinc-tin-oxide thin film transistors (SZTO-TFT) has been investigated. The SZTO channel layers were deposited by using radio frequency (RF) magnetron sputtering method with different partial pressure. The field effect mobility (${\mu}_{FE}$) increased and threshold voltage ($V_{th}$) shifted to negative direction with increasing pressure during deposition processing. As a result, oxygen vacancies generated in SZTO channel layer with increasing partial pressure resulted in negative shift in $V_{th}$ and increase in on-current.

• 반도체디스플레이기술학회지
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• 제10권4호
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• pp.43-46
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• 2011

In this study, we investigated the effects of the post Ar plasma treatment at different RF powers for various durations on electrical, structural, and optical properties of relatively thin Al-doped zinc oxide films. The sheet resistance was observed to decrease rapidly for the first 5min, beyond which the resistance apparently saturated. As the RF power increased, the grain size and the interplanar distance of (002) planes also increased. The observed decrease in sheet resistance was stated to be a consequence of Al and/or Zn interstitials as well as grain growth. It was also found that Ar plasma treatment increased the transmittance of Al-doped zinc oxide films in most of the visible light range below the blue light.

• 반도체디스플레이기술학회지
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• 제3권4호
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• pp.45-49
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• 2004

We examined large particles and filter size effects of Central Chemical Supplying (CCS) system for STI-CMP on Light Point Defects (LPDs) after polishing. As manufacturing process recently gets thinner below 0.1 um line width, it is very important to keep down post-CMP micro-scratch and LPDs in case of STI-CMP. Therefore, we must control the size distribution of large particles in a slurry. With optimization of final filter size, CCS system is one of the solutions for this issue. The oxide and nitride CMP tests were accomplished using nano-ceria slurries made by ourselves. The number of large particles in a slurry and the number of LPDs on the wafer surface after CMP were reduced with decrease of the final filter size. Oxide removal rates slightly changed according to the final filter size, showing the good performance of self-made nano ceria slurries.

• 반도체디스플레이기술학회지
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• 제3권1호
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• pp.15-20
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• 2004

Through shallow trench isolation (STI) chemical mechanical polishing (CMP) tests, we investigated the dependence of pad surface temperature on the abrasive and additive concentrations in ceria slurry under varying pressure using blanket film wafers. The pad surface temperature after CMP increased with the abrasive concentration and decreased with the additive concentration in slurries for the constant down pressure. A possible mechanism is that the additive adsorbed on the film surfaces during polishing decreases the friction coefficient, hence the pad surface temperature gets lower with increasing the additive concentration. This difference in temperature was more remarkable for the higher concentration of abrasives. In addition, in-situ measurement of spindle motor was carried out during oxide and nitride polishing. The averaged motor current for oxide film was higher than that for nitride film, meaning the higher friction coefficient.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권2호
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• pp.106-109
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• 2004

A high-density 3-transistor cell one-time programmable (OTP) ROM array using standard CMOS Gate-Oxide antifuse (AF) is proposed, fabricated, and characterized with $0.18{\mu}m$ CMOS process. The proposed non-volatile high-density OTP ROM is composed of an array of 3-T OTP cells with the 3-T consisting of an nMOS AF, a high voltage (HV) blocking transistor, and a cell access transistor, all compatible with standard CMOS technology.

• 한국반도체및디스플레이장비학회:학술대회논문집
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• 한국반도체및디스플레이장비학회 2003년도 추계학술대회 발표 논문집
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• pp.122-125
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• 2003

We investigated the effect of the abrasive and additive concentrations in Nano ceria slurry on the pad surface temperature under varying pressure through chemical mechanical polishing (CMP) test using blanket wafers. The pad surface temperature after CMP increased with the abrasive concentration and decreased with increase of the additive concentration in slurries for the constant down pressure. A possible mechanism is that the additive adsorbed on the film surface during polishing decreases the friction coefficient, hence the pad surface temperature gets lower with increase of the additive concentration. This difference of temperature was more remarkable for the higher concentration of abrasives. In addition, in-situ measurement of spindle motor was carried out during oxide and nitride polishing. The averaged motor current for oxide film was higher than that for nitride film, which means the higher friction coefficient.