• Title/Summary/Keyword: Oxide Semiconductor

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The Formation Technique of Thin Film Heaters for Heat Transfer Components (열교환 부품용 발열체 형성기술)

  • 조남인;김민철
    • Journal of the Semiconductor & Display Technology
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    • v.2 no.4
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    • pp.31-35
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    • 2003
  • We present a formation technique of thin film heater for heat transfer components. Thin film structures of Cr-Si have been prepared on top of alumina substrates by magnetron sputtering. More samples of Mo thin films were prepared on silicon oxide and silicon nitride substrates by electron beam evaporation technology. The electrical properties of the thin film structures were measured up to the temperature of $500^{\circ}C$. The thickness of the thin films was ranged to about 1 um, and a post annealing up to $900^{\circ}C$ was carried out to achieve more reliable film structures. In measurements of temperature coefficient of resistance (TCR), chrome-rich films show the metallic properties; whereas silicon-rich films do the semiconductor properties. Optimal composition between Cr and Si was obtained as 1 : 2, and there is 20% change or less of surface resistance from room temperature to $500^{\circ}C$. Scanning electron microscopy (SEM) and Auger electron spectroscopy (AES) were used for the material analysis of the thin films.

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A Study on Characteristics of Borophosphosilicate Gloss deposited by At.ospheri, Pressure Chemical Vapor Deposition (APCVD에 의란 BPSG 막질특성에 관란 연구)

  • Kim, Eui-Song;Lee, Chul-Jin;Rhieu, Ji-Hyo;Song, Sung-Hae
    • Proceedings of the KIEE Conference
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    • 1987.07a
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    • pp.561-564
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    • 1987
  • The deposition and reflow properties or BPSG film deposited by APCVD was characterized by variation of each process parameter. As deposition temperature is increased higher, deposition rate is decreased. Maximum deposition rate of BPSG film is obtained in higher 02/Hyride ratio than CVD Oxide or PSG. BPSG film shows stable dielectric properties and we obtained good planarization effect at lower reflow temperature in case of BPSG film than PSG film.

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$2{\mu}m$ CMOS P-WELL DOUBLE METAL TECHNOLOGY

  • Shin, C.H.;Ahn, K.H.;Jung, E.S.;Jin, J.H.
    • Proceedings of the KIEE Conference
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    • 1987.07a
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    • pp.424-428
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    • 1987
  • A $2{\mu}m$ CMOS P-well double metal technology has been developed. Phosphorus deep implantation and drive-in diffusion steps were utilized to prevent the low voltage bulk punch through in the short channel, 1.6[${\mu}m$] Leff, PMOS device. Double metal process with the rules of 5[${\mu}m$] 1st metal pitch and 7[${\mu}m$] 2nd metal pitch was successfully implemented by using VLTO, low temperature oxide, as on intermetal dielectric.

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Study of a New LOCOS Process Using Only Thin LPCVD Nitride (LPCVD 질화막 만을 이용한 새로운 LOCOS 공정에 관한 연구)

  • Kim, Ji-Bum;Oh, Ki-Young;Kim, Dal-Soo;Joo, Seung-Ki;Choi, Min-Sung
    • Proceedings of the KIEE Conference
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    • 1987.07a
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    • pp.429-432
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    • 1987
  • A new LOCOS (Local Oxidation of Silicon) process using a thin nitride film directly deposited on the silicon substrate by LPCVD has been developed in order to reduce the bird's beak length. SEM studies showed that nitride thickness of 50nm can decrease the bird's beak length down to 0.2um with 450nm field oxide. No crystalline defects are observed around the bird's beak after the Wright etch. A 30% improvement in current density was obtained when this new method was applied to MOS transistors (W/L*2.9/20.4) compared to conventional LOCOS process (bird's beak length=0.7um). Other various electrical parameters improved by this new simple LOCOS process are reported in this paper.

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Characteristics of P-channel SOI LDMOS Transistor with Tapered Field Oxides

  • Kim, Jong-Dae;Kim, Sang-Gi;Roh, Tae-Moon;Park, Hoon-Soo;Koo, Jin-Gun;Kim, Dae-Yong
    • ETRI Journal
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    • v.21 no.3
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    • pp.22-28
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    • 1999
  • A new tapered TEOS oxide technique has been developed to use field oxide of the power integrated circuits. It provides better uniformity of less than 3 % and reproducibility. On-resistance of P-channel RESURE (REduced SURface Field) LDMOS transistors has been optimized and improved by using a novel simulation and tapered TEOS field oxide on the drift region of the devices. With the similar breakdown voltage, at $V_{gs}$=-0.5V, the specific on-resistance of the LDMOS with the tapered field oxide is about $31.5{\Omega}{\cdot}cm^2$, while that of the LDMOS with the conventional field oxide is about $57m{\Omega}{\cdot}cm^2$.

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Epitaxial growth of Tin Oxide thin films deposited by powder sputtering method

  • Baek, Eun-Ha;Kim, So-Jin;Gang, Hyeon-Cheol
    • Proceedings of the Korean Vacuum Society Conference
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    • 2015.08a
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    • pp.185.2-185.2
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    • 2015
  • Tin Oxide (SnO2) has been widely investigated as a transparent conducting oxide (TCO) and can be used in optoelectronic devices such as solar cell and flat-panel displays. In addition, it would be applicable to fabricating the wide bandgap semiconductor because of its bandgap of 3.6 eV. There have been concentrated on the improvement of optical properties, such as conductivity and transparency, by doping Indium Oxide and Gallium Oxide. Recently, with development of fabrication techniques, high-qulaity SnO2 epitaxial thin films have been studied and received much attention to produce the electronic devices such as sensor and light-emitting diode. In this study, powder sputtering method was employed to deposit epitaxial thin films on sapphire (0001) substrates. A commercial SnO2 powder was sputtered. The samples were prepared with varying the growth parameters such as gas environment and film thickness. Then, the samples were characterized by using XRD, SEM, AFM, and Raman spectroscopy measurements. The details of physical properties of epitaxial SnO2 thin films will be presented.

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Fluorine Effects on NMOS Characteristics and DRAM Refresh

  • Choi, Deuk-Sung
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.12 no.1
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    • pp.41-45
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    • 2012
  • We observed that in chemical vapor deposition (CVD) tungsten silicide (WSix) poly gate scheme, the gate oxide thickness decreases as gate length is reduced, and it intensifies the roll-off properties of transistor. This is because the fluorine diffuses laterally from WSix to the gate sidewall oxide in addition to its vertical diffusion to the gate oxide during gate re-oxidation process. When the channel length is very small, the gate oxide thickness is further reduced due to a relative increase of the lateral diffusion than the vertical diffusion. In DRAM cells where the channel length is extremely small, we found the thinned gate oxide is a main cause of poor retention time.

Temperature Characteristics of Thermally Nitrided, Reoxidized MOS devices (열적으로 질화, 재산화된 모스 소자의 온도특성)

  • 이정석;장창덕;이용재
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 1998.11a
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    • pp.165-168
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    • 1998
  • Re-oxidized nitrided oxides which have been investigated as alternative gate oxide for Metal- Oxide -Semiconductor field effect devices were grown by conventional furnace process using pure NH$_3$ and dry $O_2$ gas, and were characterized via a Fowler-Nordheim Tunneling electron injection technique. We studied Ig-Vg characteristics, leakage current, $\Delta$Vg under constant current stress from electrical characteristics point of view and TDDB from reliability point of view of MOS capacitors with SiO$_2$, NO, ONO dielectrics. Also, we studied the effect of stress temperature (25, 50, 75, 100, and 1$25^{\circ}C$). Overall, our results indicate that optimized re-oxidized nitrided oxide shows improved Ig-Vg characteristics, leakage current over the nitrided oxide and SiO$_2$. It has also been shown that re-oxidized nitrided oxide have better TDDB performance than SiO$_2$ while maintaining a similar temperature and electric field dependence. Especially, the Qbd is increased by about 1.5 times.

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Tunnel Barrier Engineering for Non-Volatile Memory

  • Jung, Jong-Wan;Cho, Won-Ju
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.8 no.1
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    • pp.32-39
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    • 2008
  • Tunnel oxide of non-volatile memory (NVM) devices would be very difficult to downscale if ten-year data retention were still needed. This requirement limits further improvement of device performance in terms of programming speed and operating voltages. Consequently, for low-power applications with Fowler-Nordheim programming such as NAND, program and erase voltages are essentially sustained at unacceptably high levels. A promising solution for tunnel oxide scaling is tunnel barrier engineering (TBE), which uses multiple dielectric stacks to enhance field-sensitivity. This allows for shorter writing/erasing times and/or lower operating voltages than single $SiO_2$ tunnel oxide without altering the ten-year data retention constraint. In this paper, two approaches for tunnel barrier engineering are compared: the crested barrier and variable oxide thickness. Key results of TBE and its applications for NVM are also addressed.

Ultraviolet and visible light detection characteristics of amorphous indium gallium zinc oxide thin film transistor for photodetector applications

  • Chang, Seong-Pil;Ju, Byeong-Kwon
    • International journal of advanced smart convergence
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    • v.1 no.1
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    • pp.61-64
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    • 2012
  • The ultraviolet and visible light responsive properties of the amorphous indium gallium zinc oxide thin film transistor have been investigated. Amorphous indium gallium zinc oxide (a-IGZO) thin film transistor operate in the enhancement mode with saturation mobility of $6.99cm^2/Vs$, threshold voltage of 13.5 V, subthreshold slope of 1.58 V/dec and an on/off current ratio of $2.45{\times}10^8$. The transistor was subsequently characterized in respect of visible light and UV illuminations in order to investigate its potential for possible use as a detector. The performance of the transistor is indicates a high-photosensitivity in the off-state with a ratio of photocurrent to dark current of $5.74{\times}10^2$. The obtained results reveal that the amorphous indium gallium zinc oxide thin film transistor can be used to fabricate UV photodetector operating in the 366 nm.