[KSCI] Korea Science Citation Index Service

http://dx.doi.org/10.5573/JSTS.2008.8.1.032

Tunnel Barrier Engineering for Non-Volatile Memory

Jung, Jong-Wan (Department of NanoScience and Technology, Sejong University)
Cho, Won-Ju (Department of Electronic Materials Engineering, Kwangwoon University)

Publication Information

JSTS:Journal of Semiconductor Technology and Science / v.8, no.1, 2008 , pp. 32-39 More about this Journal

Abstract

Tunnel oxide of non-volatile memory (NVM) devices would be very difficult to downscale if ten-year data retention were still needed. This requirement limits further improvement of device performance in terms of programming speed and operating voltages. Consequently, for low-power applications with Fowler-Nordheim programming such as NAND, program and erase voltages are essentially sustained at unacceptably high levels. A promising solution for tunnel oxide scaling is tunnel barrier engineering (TBE), which uses multiple dielectric stacks to enhance field-sensitivity. This allows for shorter writing/erasing times and/or lower operating voltages than single $SiO_2$ tunnel oxide without altering the ten-year data retention constraint. In this paper, two approaches for tunnel barrier engineering are compared: the crested barrier and variable oxide thickness. Key results of TBE and its applications for NVM are also addressed.

Keywords

Non-volatile memory; tunnel barrier engineering; tunnel oxide; retention; VARIOT;

Citations & Related Records

Reference

1	K. Naruke et al., 'Stress induced leakage current limiting to scale down EEPROM tunnel oxide thickness,' IEDM Tech. Dig., pp. 424-427, 1988
2	'Front end processes,' in International Technology Roadmap for Semiconductors 2003 Edition. Austin, TX: Semiconductor Industry Assoc., 2003
3	K. K. Lihkarev, 'Layered tunnel barriers for nonvolatile memory devices,' Appl. Phys. Lett., vol. 73, no. 15, pp. 2137-2139, Oct. 1998 DOI ScienceOn
4	J. Buckley et al., 'Engineering of conduction band crested barriers or dielectric constant crested barriers in view of their application to floatinggate non-volatile memory devices,' Silicon Nanoelectronics Workshop, 2004
5	P. Blomme, J. D. Vosa, A. Akheyar, L. Haspeslagha, J. V. Houdt, and K. D. Meyer, 'Scalable floating gate flash memory cell with engineered tunnel dielectric and high-K $Al_2O_3$ interpoly dielectric,' IEEE Non-Volatile Semiconductor Memory Workshop, pp. 52-53, 2006
6	Hang-Ting Lue et al., 'A novel gate-injection program/erase p-channel NAND-type flash memory with high (10M cycle) endurance,' Symp. on VLSI Tech. Digest of Technical Papers, pp. 140-141, 2007
7	Sheng-Chih Lai, et al., 'MA BE-SONOS: a bandgap engineered SONOS using metal gate and $Al_2O_3$ blocking layer to overcome erase saturation,' Non-Volatile Semiconductor Memory Workshop, pp. 88-89, 2007
8	'Emerging research devices,' in International Technology Roadmap for Semiconductors 2003 Edition. Austin, TX: Semiconductor Industry Assoc., 2003
9	Julie D. Casperson, L. Douglas Bell, and Harry A. Atwater, 'Materials issues for layered tunnel barrier structures,' J. Appl. Phys., vol. 92, no. 1, pp. 261-267, 2002 DOI ScienceOn
10	'Emerging research devices,' in International Technology Roadmap for Semiconductors, Winter Conference, Makuhari, Japan, 2007
11	J. Buckley, B. De Salvo, G. Ghibaudo, M. Gely, J. F. Damlencourt, F. Martin, G. Nicotra, and S. Deleonibus, 'Investigation of $SiO_2$ / $HfO_2$ gate stacks for application to non-volatile memory devices,' Solid-State Elect., vol. 49, pp. 1833-1840, 2005 DOI ScienceOn
12	Seung Jae Baik, Siyoung Choi, U-In Chung, and Joo Tae Moon, 'Engineering on tunnel barrier and dot surface in Si nanocrystal memories,' Solid-State Elect., vol. 48, pp. 1475-1481, 2004 DOI ScienceOn
13	Hang-Ting Lue, Szu-Yu Wang, Erh-Kun Lai, Yen-Hao Shih, Sheng-Chih Lai, and Ling-Wu Yang, 'BE-SONOS: a bandgap engineered SONOS with excellent performance and reliability,' IEDM Tech. Dig., pp. 547-550, 2005
14	F. Driussi, S. Marcuzzi, P. Palestri, and L. Selmi, 'Gate current in stacked dielectrics for advanced FLASH EEPROM cells', Proceedings of ESSDERC, Grenoble, France, pp. 317-320, 2005
15	S. Lai, 'Tunnel oxide and $ETOX_TM$ flash scaling limitation,' 1998 Int'l Non-Volatile Memory Technology Conference, pp. 6-7, 1998
16	A. Furnemont, M. Rosmeulen, A. Cacciato, L. Breuil, K. De Meyer, H. Maes, and J. Van Houdt, 'Physical understanding of SANOS disturbs and VARIOT engineered barrier as a solution,' Non-Volatile Semiconductor Memory Workshop, pp. 94-95, 2007
17	M. Specht, M. Stadele, and F. Hofmann, 'Simulation of high-K tunnel barriers for nonvolatile floating gate memories,' Proc. ESSDERC Conference, pp. 599-602, 2002
18	B. Govoreanu, P. Blomme, M. Rosmeulen, J. Van Houdt, and K. De Meyer, 'VARIOT: a novel multilayer tunnel barrier concept for low-voltage nonvolatile memory devices,' IEEE Electron Device Lett., vol. 24, no. 2, pp. 99-101, Feb. 2003 DOI ScienceOn
19	Sheng-Chih Lai et al., 'Study on the erase and retention mechanisms for MONOS, MANOS, and BE-SONOS non-volatile memory devices,' Symp. on VLSI Tech. Digest of Technical Papers, pp. 1-2, 2007
20	ZongLiang Huo, JunKyu Yang, SeungHyun Lim, SeungJae Baik, Juyul Lee, JeongHee Han, In-Seok Yeo, U-In Chung, Joo Tae Moon, and Byung-II Ryu, 'Band engineered charge trap layer for highly reliable MLC flash memory,' 2007 Symposium on VLSI Technology Digest of Technical Papers, pp. 138-139, 2007
21	Y. Liu, S. Dey, S. Tang, D. Q. Kelly, J. Sarkar, and S. K. Banerjee, 'Improved performance of SiGe nanocrystal memory with VARIOT tunnel barrier,' IEEE Trans. Electron. Devices, vol. 53, no. 10, pp. 2598-2602, 2006 DOI ScienceOn

Reference

4-6	Christoph Adelmann. (2010) Chemical Vapor Deposition Atomic Layer Deposition of Gadolinium Aluminate using Gd(iPrCp)3, TMA, and O3 or H2O / 16 (4-6) , 170
2	Seongjae Cho. (2011) IEEE Transactions on Electron Devices A Charge Trap Folded nand Flash Memory Device With Band-Gap-Engineered Storage Node / 58 (2) , 288
2	Won Bo Shim. (2012) IEEE Transactions on Nanotechnology Stacked Gated Twin-Bit (SGTB) SONOS Memory Device for High-Density Flash Memory / 11 (2) , 307
1	Yoon Kim. (2012) IEEE Transactions on Electron Devices Three-Dimensional nand Flash Architecture Design Based on Single-Crystalline STacked ARray / 59 (1) , 35
6	Ki-Hyun Jang. (2013) IEEE Electron Device Letters Self-Amplified Dual Gate Charge Trap Flash Memory for Low-Voltage Operation / 34 (6) , 756
10	Sangheon Lee. (2014) IEEE Electron Device Letters Engineering Oxygen Vacancy of Tunnel Barrier and Switching Layer for Both Selectivity and Reliability of Selector-Less ReRAM / 35 (10) , 1022
8S1	Min-Hung Lee. (2014) Japanese Journal of Applied Physics Nonlinear bidirectional selector without rare materials for stackable cross-bar bipolar memory applications / 53 (8S1) , 08LE03
1558-0563	Min-Ju Ahn. (2016) IEEE Electron Device Letters Dual Gate Charge Trap Flash Memory for Highly Reliable Triple Level Cell using Capacitive Coupling Effects / (1558-0563) , 1
8	(2009) Japanese Journal of Applied Physics Extended Word-Line NAND Flash Memory / 48 (8) , 081203