• Journal of Advanced Navigation Technology
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• v.14 no.1
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• pp.20-26
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• 2010

In this paper, a frequency tripler has been designed with 100mW medium-power using P-HEMT. It is designed to obtain 7.2 GHz frequency at the output that is an integer multiple of 2.4 GHz input frequency by using nonlinear device that produces 3rd harmonic. The frequency tripler is designed by using load-pull simulation. To suppress the 2nd and fundamental, notch filter is used for the frequency tripler. The tripler is designed to obtain about 21dBm output power with 15 dBm input, i.e., 6 dB conversion gain and the suppression of 20 dBc at fundamental, and 30 dBc at the second harmonics.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.11
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• pp.865-869
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• 2011

A cantilever-type piezoelectric generator has advantages of simple structure, ease of fabrication and large displacement by transverse vibration of a beam. It is easy to control the natural frequency, and also possible to increase the output power by changing the length, width, and thickness of the generator. In particular, the length increases, the natural frequency sharply decreases, and vice versa. Hence, the natural frequency can widely be controlled by using change in the length of elastic body. In this paper, the generator was designed and fabricated to change natural frequency using the slides of the case. In addition, the generating characteristics were confirmed through finite element analyses and vibration experiment. As a result, the maximum output characteristics could be generated due to resonance phenomenon although any frequency of external force was applied.

• Journal of the Korean Society for Precision Engineering
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• v.19 no.4
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• pp.195-201
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• 2002

We propose a new scheme of high-resolution heterodyne interferometer that employs the two-axial mode He-Ne laser with an inter-mode beat frequency of 600~1000 MHz. An electronic RF-heterodyne circuit lowers the beat frequency down to 5 MHz, so that the phase change of the interferometer output is precisely measured with a displacement resolution of 0.1 nanometer without significant loss of dynamic bandwidth. A thermal control scheme is adopted to stabilize the cavity length with ainus to suppress frequency drifts caused by the phenomena of frequency pulling and polarization anisotropy of the two-axial made laser to a stability level of 2 parts in $10^9$. The two-axial mode HeNe laser yields a high output power of 2.0 mW, which allows us to perform multiple measurements of up to 10 machine axes simultaneously.

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.267-269
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• 2007

PLL(Phase Locked Loop) are widely used circuit technique in modern electronic systems. In this paper, We propose the low voltage and high speed PLL. We design the PFD(Phase Frequency Detector) by using TSPC (True Single Phase Clock) circuit to improve the performance and solve the dead-zone problem. We use CP(Charge Pump} and LP(Loop filter) for Negative feedback and current reusing in order to solve current mismatch and switch mismatch problem. The VCO(Voltage controlled Oscillator) with 5-stage differential ring oscillator is used to exact output frequency. The divider is implemented by using D-type flip flops asynchronous dividing. The frequency divider has a constant division ratio 32. The frequency range of VCO has from 200MHz to 1.1GHz and have 1.7GHz/v of voltage gain. The proposed PLL is designed by using 0.18um CMOS processor with 1.8V supply voltage. Oscillator's input frequency is 25MHz, VCO output frequency is 800MHz and lock time is 5us. It is evaluated by using cadence spectra RF tools.

• 전자공학회논문지 IE
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• v.47 no.3
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• pp.47-52
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• 2010

In this paper, a frequency tripler has been designed with 100mW medium-power using P-HEMT. It is designed to obtain 7.2GHz frequency at the output that is an integer multiple of 2.4GHz input frequency by using nonlinear device that produces 3rd harmonic. The frequency tripler is designed by using load-pull simulation. To suppress the 2nd and fundamental, notch filter is used for the frequency tripler. The tripler is designed to obtain about 21dBm output power with 15dBm input, i.e., 6dB conversion gain and the suppression of 20dBc at fundamental, and 30dBc at the second harmonics.

• Journal of IKEEE
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• v.22 no.4
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• pp.1158-1162
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• 2018

A fast-lock multiplying delay-locked loop (MDLL)-based digital clock frequency multiplier with an anti-harmonic lock capability is presented. The proposed digital frequency multiplier utilizes a new most-significant bit (MSB)-interval search algorithm to achieve fast-locking time without harmonic lock problems. The proposed digital MDLL frequency multiplier is designed in a 65nm CMOS process, and the operating output frequency range is from 1 GHz to 3 GHz. The digital MDLL provides a programmable fractional-ratio frequency multiplication ratios of N/M, where N = 1, 4, 5, 8, 10 and M = 1, 2, 3, respectively. The proposed MDLL consumes 3.52 mW at 1GHz and achieves a peak-to-peak (p-p) output clock jitter of 14.07 ps.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1246-1247
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• 2008

With recent advanced in portable electric devices, wireless sensor, MEMS and bio-Mechanics device, the new typed power supply, not conventional battery but self-powered energy source is needed. Particularly, the system that harvests from their environments are interests for use in self powered devices. For very low powered devices, environmental energy may be enough to use power source. Therefore, in other to made piezoelectric energy harvesting device, PMN-PZT thick film was formed by the screen printing method on the Ag/Pd coated alumina substrate. The layer was 8 layers and slurry where a-terpineol, ethycellulose, ferro B-75001 as Vehicle, PMN-PZT powder used are fabricated by ball mill. The output power quality was be also investigated by changing the load resistance, weight and frequency. The made piezoelectric energy harvesting device was resulted from the conditions of 33$k{\Omega}$, 0.25g, 197Hz respectively. The thick film was prepared at the condition of 2.75Vrms, and its power was 230${\mu} W$ and its thickness was 56${mu}m$. The piezoelectric energy harvesting device output voltage was increased, when the load weight, load resistance was increasing and resonance frequency was diminishing. The other side, resonance frequency was diminished, when the weight was increasing. And output power was continuously it changed by load resistance, output voltage, weight and resonance frequency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.2
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• pp.408-414
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• 2014

This paper proposes a charge-pump phase-locked loop (PLL) with 51-phase output clock of a 125 MHz target frequency. The proposed PLL uses three voltage controlled oscillators (VCOs) to generate 51-phase clock and increase of maximum operating frequency. The 17 delay-cells consists of each VCO, and a resistor averaging scheme which reduces the phase mismatch among 51-phase clock combines three VCOs. The proposed PLL uses a 65 nm 1-poly 9-metal CMOS process with 1.0 V supply. The simulated peak-to-peak 지터 of output clock is 0.82 ps at an operating frequency of 125 MHz. The differential non-linearity (DNL) and integral non-linearity (INL) of the 51-phase output clock are -0.013/+0.012 LSB and -0.033/+0.041 LSB, respectively. The operating frequency range is 15 to 210 MHz. The area and power consumption of the implemented PLL are $580{\times}160{\mu}m^2$ and 3.48 mW, respectively.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.380-383
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• 2000

This paper presents about EL(electro-luminescent) driver with inverter Inverter is constructed by using characteristic of FET and its output characteristics is analysed for the variation of gate bias frequency and load. The optimum operating condition of inverter is that the gate bias frequency of FET equal two resonant frequency of circuit.

• Journal of Sensor Science and Technology
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• v.29 no.5
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• pp.324-327
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• 2020

The impact of output conductance (g_o) on the short-circuit current-gain cut-off frequency (f_T) in In_0.8Ga_0.2As high-electron-mobility transistors (HEMTs) on an InP substrate was investigated. An attempted was made to extract the values of f_T in a simplified small-signal model (SSM) of the HEMTs, derive an analytical formula for f_T in terms of the extrinsic model parameters of the simplified SSM, which are related to the intrinsic model parameters of a general SSM, and verify its validity for devices with L_g from 260 to 25 nm. In long-channel devices, the effect of the intrinsic output conductance (g_oi) on f_T was negligible. This was because, from the simplified SSM perspective, three model parameters, such as g_{m_ext}, C_{gs_ext} and C_{gd_ext}, were weakly dependent on g_oi. However, in short-channel devices, g_oi was found to play a significant role in degrading f_T as L_g was scaled down. The increase in g_oi in short-channel devices caused a considerable reduction in g_{m_ext} and an overall increase in the total extrinsic gate capacitance, yielding a decrease in f_T with g_oi. Finally, the results were used to infer how f_T is influenced by g_oi in HEMTs, emphasizing that improving electrostatic integrity is also critical importance to benefit fully from scaling down L_g.