• Journal of the Korean Society of Industry Convergence
• /
• v.24 no.4_1
• /
• pp.377-385
• /
• 2021

High voltage direct current(HVDC) systems has been an alternative method of a power transmission to replace high voltage alternate current(HVAC), which is a traditional AC transmission method. Due to technical limitations, Line commutate converter HVDC(LCC-HVDC) was mainly used. However, result from many structural problems of LCC-HVDC, the voltage source converter HVDC(VSC-HVDC) are studied and applied recently. In this paper, after analyzing the reactive power and output voltage ripple, which are the main problems of LCC-HVDC, the characteristics of each HVDC are summarized. Based on this result, a new LCC-HVDC structure is proposed by combining LCC-HVDC with the MMC structure, which is a representative VSC-HVDC topology. The proposed structure generates lower reactive power than the conventional method, and greatly reduces the 12th harmonic, a major component of output voltage ripple. In addition, it can be easily applied to the already installed LCC-HVDC. When the proposed method is applied, the control of the reactive power compensator becomes unnecessary, and there is an advantage that the cut-off frequency of the output DC filter can be designed smaller. The validity of the proposed LCC-HVDC is verified through simulation and experiments.

• Proceedings of the KIEE Conference
• /
• 1997.07f
• /
• pp.2204-2206
• /
• 1997

A novel zero voltage and zero current switching (ZVZCS) full bridge (FB) PWM converter with a low output current ripple is proposed. The proposed circuit improve the demerits of the previously presented ZVBCS-FB-PWM converters[5-8] such as use of lossy components or additional active switches. A simple auxiliary circuit which includes neither lossy components nor active switches provides ZVZCS conditions to primary switches, ZVS for leading-leg switches and ZCS for lagging-leg switches. In addition, this proposed circuit reduces a output current ripple considerably. Many advantages including simple circuit topology, high efficiency, low cost and low current ripple make the new converter attractive far high power (> 1kW) applications.

• Journal of Power Electronics
• /
• v.12 no.2
• /
• pp.249-257
• /
• 2012

An interleaved PWM converter is proposed to implement the features of zero voltage switching (ZVS), load current sharing and ripple current reduction. The proposed converter includes two ZVS converters with a common clamp capacitor. With the shared capacitor, the charge balance of the two interleaved parts is automatically regulated under input voltage and load variations. The active-clamping circuit is used to realize the ZVS turn-on so that the switching losses on the power switches are reduced. The ZVS turn-on of all of the switching devices is achieved during the transition interval. The interleaved pulse-width modulation (PWM) operation will reduce the ripple current and the size of the input and output capacitors. The current double rectifier (CDR) is adopted in the secondary side to reduce output ripple current so that the sizes of the output chokes and capacitor are reduced. The circuit configuration, operation principles and design considerations are presented. Finally experimental results based on a 408W (24V/17A) prototype are provided to verify the effectiveness of the proposed converter.

• Journal of Power Electronics
• /
• v.4 no.1
• /
• pp.18-27
• /
• 2004

The output storage capacitor of the PFC converters is commonly designed for the selected hold-up time or the allowed output ripple voltage percentage. Nevertheless, this output capacitor is a main contribution factor to the PFC system stability. Moreover, seeking for a minimum output storage capacitor that assures the PFC desired operation under all condition, and providing the advantage of a small size and low cost is the main interesting target for engineering. Therefore, in this issue the design steps of the PFC converter have been discussed depending on three choices, output ripple, hold-up time, and stability. It is cleared that any design must take the minimum required storage capacitor for stability prospective as step-l in deign, then apply for any other specification like hold-up time or ripple percentage.

• Journal of Power Electronics
• /
• v.15 no.3
• /
• pp.587-601
• /
• 2015

A high step-up dc-dc converter is proposed for photovoltaic power systems in this paper. The proposed converter consists of an input current doubler, a symmetrical switched-capacitor doubler and an active-clamp circuit. The input current doubler minimizes the input current ripple. The symmetrical switched-capacitor doubler is composed of two symmetrical quasi-resonant switched-capacitor circuits, which share the leakage inductance of the transformer as a resonant inductor. The rectifier diodes (switched-capacitor circuit) are turned off at the zero current switching (ZCS) condition, so that the reverse-recovery problem of the diodes is removed. In addition, the symmetrical structure results in an output voltage ripple reduction because the voltage ripples of the charge/pump capacitors cancel each other out. Meanwhile, the voltage stress of the rectifier diodes is clamped at half of the output voltage. In addition, the active-clamp circuit clamps the voltage surges of the switches and recycles the energy of the transformer leakage inductance. Furthermore, pulse-width modulation plus phase angle shift (PPAS) is employed to control the output voltage. The operation principle of the converter is analyzed and experimental results obtained from a 400W prototype are presented to validate the performance of the proposed converter.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.8 no.5
• /
• pp.1068-1073
• /
• 2004

5 V/500 mA transless type power module was designed by using a semiconductor switching technique for a small-sized electric power source. It used voltage drop type chopper method, and is composed of switching circuit, control circuit, voltage detect circuit, and constant voltage circuit. The switching power module which is designed in this study, showed load regulation of 0.2 V, line regulation of 0.1 V, output ripple of 85 mVp-p, switching frequency of 64.7 kHz, maximum power efficiency of 58 %, and satisfied its reliability and EMC test.

• Proceedings of the KIEE Conference
• /
• 1993.07b
• /
• pp.867-869
• /
• 1993

In generally Boost Converter is used for Fuel Cell System. Because the output voltage of fuel cell is too small and greatly depends on the load condition, Boost Converter are required to boost and regulate the Fuel Cell voltage for per conversion efficiency. In this Paper, 6-phase Boost Converter is used to boost the Fuel Cell Voltage and regulate the output voltage. Multi phase converter hag some advantages such as low ripple and filter sine. About the Peak Current Control and compare of the Ripple Current of Boost Converter, we have studied.

• Journal of the Korean Solar Energy Society
• /
• v.39 no.2
• /
• pp.81-92
• /
• 2019

When Photovoltaic inverter is connected to grid and used as PVPCS (Photovoltaic Power Conditioning System), 120 Hz AC ripple occurs at the dc-link capacitor voltage. This AC ripple reduces the efficiency of PVPCS and shortens the lifetime of the capacitor. In this paper, we design a notch filter to remove AC ripple. As a result, the AC voltage ripple was removed from the dc link and the THD of the PVPCS output current with the notch filter was lowered. This notch filter is determined by the damping coefficient, the bandwidth coefficient, and the switching frequency. Among these, the switching frequency determines the switching loss and the size of the LC filter, and the PVPCS with the high switching frequency has a greater efficiency loss due to the switching loss than the efficiency improvement by the notch filter. Therefore, it is important to set the optimum switching frequency in the PVPCS with the notch filter applied. In this paper, THD and switching loss of PVPCS output current with notch filter are calculated through simulation, and cost function to calculate optimum switching frequency through data is proposed.

• Journal of Power Electronics
• /
• v.15 no.6
• /
• pp.1429-1437
• /
• 2015

A new parallel hybrid soft switching converter with low circulating current losses during the freewheeling state and a low output current ripple is presented in this paper. Two circuit modules are connected in parallel using the interleaved pulse-width modulation scheme to provide more power to the output load and to reduce the output current ripple. Each circuit module includes a three-level converter and a half-bridge converter sharing the same lagging-leg switches. A resonant capacitor is adopted on the primary side of the three-level converter to reduce the circulating current to zero in the freewheeling state. Thus, the high circulating current loss in conventional three-level converters is alleviated. A half-bridge converter is adopted to extend the ZVS range. Therefore, the lagging-leg switches can be turned on under zero voltage switching from light load to full load conditions. The secondary windings of the two converters are connected in series so that the rectified voltage is positive instead of zero during the freewheeling interval. Hence, the output inductance of the three-level converter can be reduced. The circuit configuration, operation principles and circuit characteristics are presented in detail. Experiments based on a 1920W prototype are provided to verify the effectiveness of the proposed converter.

• IEIE Transactions on Smart Processing and Computing
• /
• v.4 no.5
• /
• pp.371-378
• /
• 2015

In this paper, a different type of pulse width modulation (PWM) control scheme for a buck converter is introduced. The proposed buck converter uses PWM with frequency hopping and a low quiescent.current low dropout (LDO) voltage regulator with a power supply rejection ratio enhancer to reduce high spurs, harmonics and output voltage ripples. The low quiescent.current LDO voltage regulator is not described in this paper. A three-bit binary-to-thermometer decoder scheme and voltage ripple controller (VRC) is implemented to achieve low voltage ripple less than 3mV to increase the efficiency of the buck converter. An internal clock that is synchronized to the internal switching frequency is used to set the hopping rate. A center frequency of 2.5MHz was chosen because of the bluetooth low energy (BLE) application. This proposed DC-DC buck converter is available for low-current noise-sensitive loads such as BLE and radio frequency loads in portable communications devices. Thus, a high-efficiency and low-voltage ripple is required. This results in a less than 2% drop in the regulator's efficiency, and a less than 3mV voltage ripple, with -26 dBm peak spur reduction operating in the buck converter.