• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.29 no.10
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• pp.73-82
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• 2015

This paper proposes an ripple reduction algorithm and analyzes the effects of offset and scale errors generated by voltage sensor while measuring grid voltage in grid-tied single-phase inverters. Generally, the grid-connected inverter needs to detect the phase angle information by measuring grid voltage for synchronization, so that the single-phase inverter can be accurately driven based on estimated phase angle information. However, offset and scale errors are inevitably generated owing to the non-linear characteristics of voltage sensor and these errors affect that the phase angle includes 1st harmonic component under using SRF-PLL(Synchronous Reference Frame - Phase Locked Loop) system for detecting grid phase angle. Also, the performance of the overall system is degraded from the distorted phase angle including the specific harmonic component. As a result, in this paper, offset and scale error due to the voltage sensor in single-phase grid connected inverter under SRF-PLL is analyzed in detail and proportional resonant controller is used to reduce the ripples caused by the offset error. Especially, the integrator output of PI(Proportional Integral) controller in SRF-PLL is selected as an input signal of the proportional resonant controller. Simulation and experiment are performed to verify the effectiveness of the proposed algorithm.

• Journal of IKEEE
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• v.23 no.3
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• pp.1061-1067
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• 2019

In this paper, a highly integrated 3-channel DC-DC converter is designed using power transistor width scaling (PTWS). For positive voltage, $V_{POS}$, a boost converter is designed using the set-time variable pulse width modultaion (SPWM) dual-mode and PTWS to improve efficiency at light load. For negative voltage, $V_{NEG}$, a 0.5 x regulated inverting charge pump is designed with pulse skipping modulation (PSM) controller to reduce power consumption, and for an additional positive voltage, $V_{AVDD}$, a LDO circuit is designed. The proposed DC-DC converter has been designed using a $0.18{\mu}m$ BCDMOS process. Simulation results show that the proposed converter has power efficiency of 56%~90% for load current range of 1 mA~70 mA and output ripple voltage less than 5 mV at positive voltage.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.21 no.6
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• pp.117-125
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• 2007

Recently, a fuel cell with low voltage and high current output characteristics is remarkable for new generation system. It needs both a DC-DC step-up converter and DC-AC inverter to be used in fuel cell generation system. Therefor, this paper, consists of an isolated DC-DC converter to boost the fuel cell voltage 380[VDC] and a PWM inverter with LC filter to convent the DC voltage to single-phase 220[VAC]. Expressly, The fuel cell system which it proposes DC-DC the efficient converter used PWM the phase transient control law and it depended to portion resonance ZVS switching, loss peek voltage and electric current of realization under make schedule, switching frequency anger and the switch reduction. And mind benevolence it sprouted 2 in stop circuit and it added and a direct current voltage and the electric current where the ingredient is reduced in load side ripple stable under make whom it will be able to supply. Besides the efficiency of 92[%]is obtained over the wide output voltage regulation ranges and load variations. Also, under make over together the result leads simulation and test, the propriety confirmation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.1-7
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• 2008

This paper proposes 3.3V input and 1.8V output voltage mode step-down DC-DC buck converter for wireless mobile system which is designed in a standard 0.35$\mu$m CMOS process. The proposed capacitor multiplier method can minimize error amplifier compensation block size by 30%. It allows the compensation block of DC-DC converter be easily integrated on a chip. Also, we improve efficiency to 3% using low power buffer. Measurement result shows that the circuit has less than 1.17% output ripple voltage and maximum 83.9% power efficiency.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.24 no.5
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• pp.136-144
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• 2010

This paper presents the two-switch interleaved active clamp forward converter, which is mainly composed of two active clamp forward converters. Only two switches are required, and each one is the auxiliary switch for the other. So, the circuit complexity and cost are reduced and control is more simple. An additional resonant inductance is employed to achieve ZVS(Zero-Voltage-Switching) during the dead times. Interleaved output inductor currents diminish the voltage and current ripple. Accordingly, the smaller output filter and capacitors lower the converter volume. This research proposed the Two-switch interleaved Active Clamp Forward Converter characteristic. The principle of operation, feature and design considerations is illustrated and the validity of verified through the experiment with a 160[W] based experimental circuit.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.9
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• pp.21-26
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• 2016

This paper presents a step-down DC-DC buck converter with a CCM/DCM dual-mode function for the internal power stage of portable electronic device. The proposed converter that is operated with a high frequency of 1 MHz consists of a power stage and a control block. The power stage has a power MOS transistor, inductor, capacitor, and feedback resistors for the control loop. The control part has a pulse width modulation (PWM) block, error amplifier, ramp generator, and oscillator. In this paper, an external capacitor for compensation has been replaced with a multiplier equivalent CMOS circuit for area reduction of integrated circuits. In addition, the circuit includes protection block, such as over voltage protection (OVP), under voltage lock out (UVLO), and thermal shutdown (TSD) block. The proposed circuit was designed and verified using a $0.18{\mu}m$ CMOS process parameter by Cadence Spectra circuit design program. The SPICE simulation results showed a peak efficiency of 94.8 %, a ripple voltage of 3.29 mV ripple, and a 1.8 V output voltage with supply voltages ranging from 2.7 to 3.3 V.

• Journal of Power Electronics
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• v.16 no.3
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• pp.1209-1217
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• 2016

This paper presents a novel charge pump scheme that combines the advantages of Fibonacci and Dickson charge pumps to obtain 30 V voltage for display driver integrated circuit application. This design only requires four external capacitors, which is suitable for a small-package application, such as smart card displays. High-amplitude (<6.6 V) clocks are produced to enhance the gate drive of a Dickson charge pump and improve the system's current drivability by using a voltage-doubler charge pump with a pulse skip regulator. This regulation engages many middle-voltage devices, and approximately 30% of chip size is saved. Further optimization of flying capacitors tends to decrease the total chip size by 2.1%. A precise and simple model for a one-stage Fibonacci charge pump with current load is also proposed for further efficiency optimization. In a practical design, its voltage error is within 0.12% for 1 mA of current load, and it maintains a 2.83% error even for 10 mA of current load. This charge pump is fabricated through a 0.11 μm 1.5 V/6 V/32 V process, and two regulators, namely, a pulse skip one and a linear one, are operated to maintain the output of the charge pump at 30 V. The performances of the two regulators in terms of ripple, efficiency, line regulation, and load regulation are investigated.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.4
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• pp.504-510
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• 2017

This paper presents an AC-DC power module design and evaluates its efficiency and reliability when used for electronics appliances. This power module consists of a PWM control IC, power MOSFETs, a transformer and several passive devices. The module was tested at an input voltage of 220V (RMS) (frequency 60 Hz). A test was conducted in order to evaluate the operation and power efficiency of the module, as well as the reliability of its protection functions, such as its over-current protection (OVP), overvoltage protection (OVP) and electromagnetic interference (EMI) properties. Especially, we evaluated the thermal shut-down protection (TSP) function in order to assure the operation of the module under high temperature conditions. The efficiency and reliability measurement results showed that at an output voltage of 5 V, the module had a ripple voltage of 200 mV, power efficiency of 73 % and maximum temperature of $80^{\circ}C$ and it had the ability to withstand a stimulus of high input voltage of 4.2 kV during 60 seconds.

• Journal of the Korean Society of Marine Environment & Safety
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• v.25 no.6
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• pp.802-808
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• 2019

DC motors are used extensively on shipboard, including as the ship's winch operating motor, owing to their simple speed control and excellent output torque characteristics. Moreover, they were used as propulsion motors in the early days of electric propulsion ships. However, mechanical rectifiers, such as brushes, used in DC motors have certain disadvantages. Hence, brushless DC (BLDC) motors are increasingly being used instead. While the electrical characteristics of both types of motors are similar, BLDC motors employ electronic rectifying devices, which use semiconductor elements, instead of mechanical rectifying devices. The inverter system for driving conventional BLDC motors uses a two-phase excitation method so that the waveform of the back electromotive force becomes trapezoidal. This causes harmonics and torque ripple in the phase current switching period in which the winding wire through which the current flows is changed. Researchers have studied and presented various methods to reduce the harmonics and torque ripple. This study applies a cascaded H-bridge multilevel inverter, which implements a proportional-integral speed current controller algorithm in the driving circuit of the BLDC motor for electric propulsion ships using a power analysis program. The simulation results of the modeled BLDC motor show that the driving method of the proposed BLDC motor improves the voltage waveform of the input side of the motor and remarkably reduces the harmonics and torque ripple compared with the conventional driving method.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.10
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• pp.40-47
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• 2016

In this paper, a dual mode buck converter with an ability to change mode is proposed, which is suitable particularly for portable device. The problem of conventional mode control circuit is affected by load variation condition such as suddenly or slowly. To resolve this problem, the mode control was designed with slow clock method. Also, when change from the PFM(Pulse Frequency Modulation) mode to the PWM(Pulse Width Modulation) mode, to use the counter to detect a high load. And the user can select mode transition point in load range from 20mA to 90mA by 3 bit digital signal. The circuits are implemented by using BCDMOS 0.18um 2-polt 3-metal process. Measurement environment are input voltage 3.7V, output voltage 1.2V and load current range from 10uA to 500mA. And measurement result show that the peak efficiency is 86% and ripple voltage is less 32mV.