• Journal of Power Electronics
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• v.16 no.2
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• pp.621-630
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• 2016

In this paper, a single current sensor technique (SCST) is proposed for single-phase full-bridge inverters. The proposed SCST measures the currents of multiple branches at the same time, and reconstructs the average inductor, capacitor, and load current in a single switching cycle. Since all of the branches' current in the LC filter and the load are obtained using the SCST, both the inductor and the capacitor current feedback schemes can be selectively applied while taking advantages of each other. This paper also analyzes both of the current feedback schemes from the view point of the closed-loop output impedance. The proposed SCST and the analysis in this paper are verified through experiments on a 3kVA single-phase uninterruptible power supply (UPS).

• The Transactions of the Korean Institute of Electrical Engineers
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• v.43 no.2
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• pp.259-267
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• 1994

This paper describes a current control of a single-phase PWM inverter. The proposed PWM inverter utilizes the instantaneous control method which is based on the real-time digital feedback control and the microprocessor-based deadbeat control. The deadbeat current controller is proposed to control the output current regardless of load component variations by the same method as voltage control. That is, in current control, with a very short sampling time and the successive feedback of the output current, the load current is mainly effected by the magnitude of load impedance rather than load component, the load current is mainly effected by the magnitude of load impedance rather than load component. Therefore, by treating the load as an impedance, the system's order is reduced and the instantaneous current control using the proposed deadeat controller is simplified.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.10
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• pp.5116-5131
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• 2017

This paper studies the radio frequency to direct current (RF-DC) conversion efficiency of rectennas applicable to wireless power transfer systems, where multiple receive antennas are arranged in serial, parallel or cascaded form. To begin with, a 2.45 GHz dual-diode rectifier is designed and its equivalent linear model is applied to analyze its output voltage and current. Then, using Advanced Design System (ADS), it is shown that the rectifying efficiency is as large as 66.2% in case the input power is 15.4 dBm. On the other hand, to boost the DC output, three composite rectennas are designed by inter-connecting two dual-diode rectifiers in serial, parallel and cascade forms; and their output voltage and current are investigated using their respective equivalent linear models. Simulation and experimental results demonstrate that all composite rectennas have almost the same RF-DC conversion efficiency as the dual-diode rectifier, yet the output of voltage or current can be significantly increased; in particular, the cascade rectenna obtains the highest rectifying efficiency.

• Proceedings of the KIPE Conference
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• 2004.07a
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• pp.341-345
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• 2004

A high efficiency and low device stress voltage and current clamping BVS PWM asymmetrical half bridge converter is proposed in this paper. To achieve the ZVS of power switches along the wide load range, the transformer leakage inductor $L_{Ikg}$ is increased. Then, to solve the problem related to ringing in the secondary rectifier caused by the resonance between $L_{Ikg}$ and rectifier junction capacitors, the proposed converter employs a voltage and current clamping cell, which helps voltages and currents of rectifier diodes to be clamped at the output voltage and output current, respectively. Therefore, no RC-snubber for rectifier diodes is needed and a high efficiency as well as low noise output voltage can be realized. In addition, since all energy stored in $L_{Ikg}$ is transferred to the output side, the circulating energy problem can be effectively solved and duty loss does net exist. The operational principle, theoretical analysis, and design considerations are presented. To confirm the operation, validity, and features of the proposed circuit, experimental results from a 425W, 385-170Vdc prototype are presented.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.1
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• pp.11-19
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• 2007

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit which becomes more serious problem due to the thin gate oxide and small threshold voltage in nanometer CMOS technology and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm predictive CMOS technology and uses a 0.9V power supply voltage. The simulation results show that the proposed PLL achieves a 88% jitter reduction at 440MHz output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of $40M{\sim}725MHz$ with a multiplication range of 11023, and the RMS and peak-to-peak jitter are 5ps and 42.7ps, respectively.

• Journal of Power Electronics
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• v.13 no.5
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• pp.896-908
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• 2013

Under high grid impedance conditions, it is difficult to guarantee the stability of grid-connected inverters with an LCL filter designed based on ideal grid conditions. In this paper, the theoretical basis for output impedance calculation is introduced. Based on the small-signal model, the d-d channel closed-loop output impedance models adopting the converter-side current control method and the grid-side current control method are derived, respectively. Specifically, this paper shows how to simplify the stability analysis which is usually complemented based on the generalized Nyquist stability criterion (GNC). The stability of each current-controlled grid-connected system is analyzed via the proposed simplified method. Moreover, the influence of the LCL parameters on the stability margin of grid-connected inverter controlled with converter-side current is studied. It is shown that the stability of grid-connected systems is fully determined by the d-d channel output admittance of the grid-connected inverter and the inductive component of the grid impedance. Experimental results validate the proposed theoretical stability analysis.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• v.2B no.3
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• pp.81-89
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• 2002

The sensorless AC motor drive is a popular topic of study due to the cost and reliability of speed and position sensors. Most sensorless algorithms are based on the mathematical modeling of motors including electrical variables such as phase current and voltage. Therefore, the accuracy of such variables largely affects the performance of the sensorless AC motor drive. However, the output voltage of the SVPWM-VSI, which is widely used in sensorless AC motor drives, has considerable errors. In particular, the SVPWM-VSI is error-prone in the low speed range because the constant DC link voltage causes poor resolution in a low output voltage command and the output voltage is distorted due to dead time and voltage drop. This paper investigates a novel high-performance strategy for overcoming these problems in a sensorless ac motor drive. In this paper, a variation of the DC link voltage and a direct compensation for dead time and voltage drop are proposed. The variable DC link voltage leads to an improved resolution of the inverter output voltage, especially in the motor's low speed range. The direct compensation for dead time and voltage drop directly calculates the duration of the switching voltage vector without the modification of the reference voltage and needs no additional circuits. In addition, the proposed strategy reduces a current ripple, which deteriorates the accuracy of a monitored current and causes torque ripple and additional loss. Simulation and experimentation have been performed to verify the proposed strategy.

• Proceedings of the KIEE Conference
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• 2001.04a
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• pp.244-246
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• 2001

In a full digital implementation of a current regulator, the voltage output is inevitably delayed due to arithmetic calculation and PWM. In case of the synchronous frame current regulator, the time delay is accompanied by the rotation of frame. In some applications in which the ratio of sampling frequency to output frequency is not high enough, such as high power drive or super high-speed drive, it is known that the effect of rotation of frame during the delay time causes phase and magnitude error in the voltage output. The error degrades the dynamic performance and can bring about the instability of current regulator at high speed. It is also intuitively known that advancing the phase of voltage output can mitigate the instability. In this paper, the instability problems are studied analytically and a compensation method for the error has been proposed. By means of computer simulation and complex root locus analysis, comparative study with conventional methods is carried out and the effectiveness of proposed method is verified.

• Journal of Power Electronics
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• v.15 no.4
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• pp.1131-1138
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• 2015

This study presents an input-powered high-efficiency interface circuit for energy harvesting systems, and introduces a zero standby power design to reduce power consumption significantly while removing the external power supply. This interface circuit is composed of two stages. The first stage voltage doubler uses a positive feedback control loop to improve considerably the conversion speed and efficiency, and boost the output voltage. The second stage active diode adopts a common-grid operational amplifier (op-amp) to remove the influence of offset voltage in the traditional comparator, which eliminates leakage current and broadens bandwidth with low power consumption. The system supplies itself with the harvested energy, which enables it to enter the zero standby mode near the zero crossing points of the input current. Thereafter, high system efficiency and stability are achieved, which saves power consumption. The validity and feasibility of this design is verified by the simulation results based on the 65 nm CMOS process. The minimum input voltage is down to 0.3 V, the maximum voltage efficiency is 99.6% with a DC output current of 75.6 μA, the maximum power efficiency is 98.2% with a DC output current of 40.4 μA, and the maximum output power is 60.48 μW. The power loss of the entire interface circuit is only 18.65 μW, among which, the op-amp consumes only 2.65 μW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.11
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• pp.836-845
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• 2001

A Novel fully-differential bipolar current subtracter(FCS) and its application to current controlled current amplifier(CCCA) for high-accuracy current-mode signal processing were designed. To obtain full-differential current output, the FCS was symmetrically composed of two current follower with low current-input impedance. The CCCA to control output current by the bias current was consisted of the subtracter and a current gain amplifier(CGA) with single-ended current output.. The simulation result shows that the FCS has current-input impedance of 5 Ω and a good linearity. The CCCA has 3-dB cutoff frequency of 20 MHz for the range over bias current 100 $\mu$A to 20 mA. The power dissipation of the FCS and CCCA are 1.8 mW and 3 mW, respectively.