• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.48-57
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• 2006

This work describes a 12b 200KHz 0.52mA $0.47mm^2$ algorithmic ADC for sensor applications such as motor controls, 3-phase power controls, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels for high integration employs a folded-cascode architecture to achieve a required DC gain and a sufficient phase margin. A signal insensitive 3-D fully symmetrical layout with critical signal lines shielded reduces the capacitor and device mismatch of the MDAC. The improved switched bias power-reduction techniques reduce the power consumption of analog amplifiers. Current and voltage references are integrated on the chip with optional off-chip voltage references for low glitch noise. The employed down-sampling clock signal selects the sampling rate of 200KS/s or 10KS/s with a reduced power depending on applications. The prototype ADC in a 0.18um n-well 1P6M CMOS technology demonstrates the measured DNL and INL within 0.76LSB and 2.47LSB. The ADC shows a maximum SNDR and SFDR of 55dB and 70dB at all sampling frequencies up to 200KS/s, respectively. The active die area is $0.47mm^2$ and the chip consumes 0.94mW at 200KS/s and 0.63mW at 10KS/s at a 1.8V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.75-85
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• 2009

This work proposes a 13b 100MS/s 0.13um CMOS ADC for 3G communication systems such as two-carrier W-CDMA applications simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs a four-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. Area-efficient high-speed high-resolution gate-bootstrapping circuits are implemented at the sampling switches of the input SHA to maintain signal linearity over the Nyquist rate even at a 1.0V supply operation. The cascode compensation technique on a low-impedance path implemented in the two-stage amplifiers of the SHA and MDAC simultaneously achieves the required operation speed and phase margin with more reduced power consumption than the Miller compensation technique. Low-glitch dynamic latches in sub-ranging flash ADCs reduce kickback-noise referred to the differential input stage of the comparator by isolating the input stage from output nodes to improve system accuracy. The proposed low-noise current and voltage references based on triple negative T.C. circuits are employed on chip with optional off-chip reference voltages. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.70LSB and 1.79LSB, respectively. The ADC shows a maximum SNDR of 64.5dB and a maximum SFDR of 78.0dB at 100MS/s, respectively. The ABC with an active die area of $1.22mm^2$ consumes 42.0mW at 100MS/s and a 1.2V supply, corresponding to a FOM of 0.31pJ/conv-step.

• Radiation Oncology Journal
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• v.26 no.4
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• pp.195-203
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• 2008

Purpose: To investigate the treatment outcome and failure patterns after definitive chemoradiation therapy in locally advanced, unresectable esophageal cancer. Materials and Methods: From February 1994 to December 2002, 168 patients with locally advanced unresectable or medically inoperable esophageal cancer were treated by definitive chemoradiation therapy. External beam radiation therapy (EBRT) ($42{\sim}46\;Gy$) was delivered to the region encompassing the primary tumor and involved lymph nodes, while the supraclavicular fossa and celiac area were included in the treatment area as a function of disease location. The administered cone-down radiation dose to the gross tumor went up to $54{\sim}66\;Gy$, while the fraction size of the EBRT was 1.8-2.0 Gy/fraction qd or 1.2 Gy/fraction bid. An optional high dose rate (HDR) intraluminal brachytherapy (BT) boost was also administered (Ir-192, $9{\sim}12\;Gy/3{\sim}4\;fx$). Two cycles of concurrent FP chemotherapy (5-FU $1,000\;mg/m^2$/day, days $2{\sim}6$, $30{\sim}34$, cisplatin $60\;mg/m^2$/day, days 1, 29) were delivered during radiotherapy with the addition of two more cycles. Results: One hundred sixty patients were analyzable for this review [median follow-up time: 10 months (range $1{\sim}149$ months)). The number of patients within AJCC stages I, II, III, and IV was 5 (3.1%), 38 (23.8%), 68 (42.5%), and 49 (30.6%), respectively. A HDR intraluminal BT was performed in 26 patients. The 160 patients had a median EBRT radiation dose of 59.4 Gy (range $44.4{\sim}66$) and a total radiation dose, including BT, of 60 Gy (range $44.4{\sim}72$), while 144 patients received a dose higher than 40 Gy. Despite the treatment, the disease recurrence rate was 101/160 (63.1%). Of these, the patterns of recurrence were local in 20 patients (12.5%), persistent disease and local progression in 61 (38.1%), distant metastasis in 15 (9.4%), and concomitant local and distant failure in 5 (3.1%). The overall survival rate was 31.8% at 2 years and 14.2% at 5 years (median 11.1 months). Disease-free survival was 29.0% at 2 years and 22.7% at 5 years (median 10.4 months). The response to treatment and N-stage were significant factors affecting overall survival. In addition, total radiation dose (${\geq}50\;Gy$ vs. < 50 Gy), BT and fractionation scheme (qd. vs. bid.) were not significant factors for overall survival and disease-free survival. Conclusion: Survival outcome after definitive chemoradiation therapy in unresectable esophageal cancer was comparable to those of other series. The main failure pattern was local recurrence. Survival rate did not improve with increased radiation dose over 50 Gy or the use of brachytherapy or hyperfractionation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.58-68
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• 2006

This work proposes a 10b 250MS/s $1.8mm^2$ 85mW 0.13um CMOS A/D Converter (ADC) for high-performance integrated systems such as next-generation DTV and WLAN simultaneously requiring low voltage, low power, and small area at high speed. The proposed 3-stage pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The input SHA maintains 10b resolution with either gate-bootstrapped sampling switches or nominal CMOS sampling switches. The SHA and two MDACs based on a conventional 2-stage amplifier employ optimized trans-conductance ratios of two amplifier stages to achieve the required DC gain, bandwidth, and phase margin. The proposed signal insensitive 3-D fully symmetric capacitor layout reduces the device mismatch of two MDACs. The low-noise on-chip current and voltage references can choose optional off-chip voltage references. The prototype ADC is implemented in a 0.13um 1P8M CMOS process. The measured DNL and INL are within 0.24LSB and 0.35LSB while the ADC shows a maximum SNDR of 54dB and 48dB and a maximum SFDR of 67dB and 61dB at 200MS/s and 250MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 85mW at 250MS/s at a 1.2V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.60-68
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• 2009

This work proposes a 10b 200MS/s 65nm CMOS ADC for high-definition video systems such as HDTV requiring high resolution and fast operating speed simultaneously. The proposed ADC employs a four-step pipeline architecture to minimize power consumption and chip area. The input SHA based on four capacitors reduces the output signal range from $1.4V_{p-p}$ to $1.0V_{p-p}$ considering high input signal levels at a low supply voltage of 1.2V. The proposed three-stage amplifiers in the input SHA and MDAC1 overcome the low output resistance problem as commonly observed in a 65nm CMOS process. The proposed multipath frequency-compensation technique enables the conventional RNMC based three-stage amplifiers to achieve a stable operation at a high sampling rate of 200MS/s. The conventional switched-bias power-reduction technique in the sub-ranging flash ADCs further reduces power consumption while the reference generator integrated on chip with optional off-chip reference voltages allows versatile system a locations. The prototype ADC in a 65nm CMOS technology demonstrates a measured DNL and INL within 0.19LSB and 0.61LSB, respectively. The ADC shows a maximum SNDR of 54.BdB and 52.4dB and a maximum SFDR of 72.9dB and 64.8dB at 150MS/S and 200MS/s, respectively. The proposed ADC occupies an active die area of $0.76mm^2$ and consumes 75.6mW at a 1.2V supply voltage.