• Current Optics and Photonics
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• v.7 no.5
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• pp.557-561
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• 2023

Ultralow-noise soliton pulse generation over a wider Fourier frequency range is highly desirable for many high-precision applications. Here, we realize a low-phase-noise soliton pulse generation by transferring the low phase noise of a mode-locked laser to a silica microcomb. A 21.956-GHz and a 9.9167-GHz Kerr soliton combs are synchronized to a 2-GHz and a 2.5-GHz mode-locked laser through a fractional optoelectronic phase-locked loop, respectively. The phase noise of the microcomb was suppressed by up to ~40 dB at 1-Hz Fourier frequency. This result provides a simple method for low-phase-noise soliton pulse generation, thereby facilitating extensive applications.

• ETRI Journal
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• v.21 no.3
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• pp.1-5
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• 1999

A clock and data recovery circuit with a phase-locked loop for 10 Gb/s optical transmission system was realized in a hybrid IC form. The quadri-correlation architecture is used for frequency-and phase-locked loop. A NRZ-to-PRZ converter and a 360 degree analogue phase shifter are included in the circuit. The jitter characteristics satisfy the recommendations of ITU-T. The capture range of 150 MHz and input voltage sensitivity of 100 mVp-p were showed. The temperature compensation characteristics were tested for the operating temperature from -10 to $60^{\circ}C$ and showed no increase of error. This circuit was adopted for the 10 Gb/s transmission system through a normal single-mode fiber with the length of 400 km and operated successfully.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.6
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• pp.71-78
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• 1999

In this paper, a new model for optical phase-locked loop(OPLL) is proposed that includes VCO laser frequency response as well as loop propagation delay. It is found that both of them greatly affect the OPLL performance. Our model can be used for realizing high-performance microwave-range OPLL.

• Korean Journal of Optics and Photonics
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• v.10 no.6
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• pp.507-511
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• 1999

A 10 GHz timing extracted signal which is phase-locked to a 10 Gbit/s mode-locked optical fiber laser pulse train is obtained using a tour-wave-mixing signal in semiconductor optical amplifier. The phase-locked loop wm, demonstrated ~Llccessful1y over 8 hours and found to have the lock-in frequency range of 30 KHz. 0 KHz.

• ETRI Journal
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• v.30 no.2
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• pp.275-281
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• 2008

A 40 Gb/s clock and data recovery (CDR) module for a fiber-optic receiver with improved phase-locked loop (PLL) circuits has been successfully implemented. The PLL of the CDR module employs an improved D-type flip-flop frequency acquisition circuit, which helps to stabilize the CDR performance, to obtain faster frequency acquisition, and to reduce the time of recovering the lock state in the event of losing the lock state. The measured RMS jitter of the clock signal recovered from 40 Gb/s pseudo-random binary sequence ($2^{31}-1$) data by the improved PLL clock recovery module is 210 fs. The CDR module also integrates a 40 Gb/s D-FF decision circuit, demonstrating that it can produce clean retimed data using the recovered clock.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.191-196
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• 2005

A low-cost, high-performance 40 Gb/s clock recovery module using a phase-locked loop(PLL) for a 40 Gb/s optical receiver has been designed and implemented. It consists of a clock recovery circuit, a RF mixer and frequency discriminator for phase/frequency detection, a DR-VCO, a phase shifter, and a hold circuit. The recovered 40 GHz clock is synchronized with a stable 10 GHz DR-VCO. The clock stability and jitter characteristics of the implemented PLL-based clock recovery module has shown to significantly improve the performance of the conventional open-loop type clock recovery module with DR filter. The measured peak-to-peak RMS jitter is about 230 fs. When input signal is dropped, the 40 GHz clock is generated continuously by hold circuit. The implemented clock recovery module can be used as a low-cost and high-performance receiver module for 40 Gb/s commercial optical network.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.3
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• pp.238-242
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• 1988

It is analyzed how performance of phase-locked loop driven by photodetector current in optical receiver will be changed under the condition that Gaussian thermal noise, pattern noise and shot noise are present and the loop has the nonzero detuning frequency. The phase error variance cahnges with the circuit configuration and the produced noise models. The analyzed results are applied to the previously implemented 90.194Mbps optic system whose loop filter is the improved active noninverting 1-st order lag-lead type.

• Current Optics and Photonics
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• v.7 no.6
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• pp.708-713
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• 2023

A robust all-fiber nonlinear amplifying loop-mirror-based mode-locked femtosecond laser is demonstrated. Power-dependent nonlinear phase shift in a Sagnac loop enables stable and power-efficient mode-locking working as an artificial saturable absorber. The pump power is adjusted to achieve the lowest intensity noise for stable long-term operation. The minimum pump power for mode-locking is 180 mW, and the optimal pump power is 300 mW. The lowest integrated root-mean-square relative intensity noise of a free-running mode-locked laser is 0.009% [integration bandwidth: 1 Hz-10 MHz]. The long-term repetition-rate instability of a free-running mode-locked laser is 10^-7 over 1,000 s averaging time. The repetition-rate phase noise scaled at 10-GHz carrier is -122 dBc/Hz at 10 kHz Fourier frequency. The demonstrated method can be applied as a seed source in high-precision real-time mid-infrared molecular spectroscopy.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2008.11a
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• pp.135-136
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• 2008

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.4
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• pp.188-193
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• 2003

This paper describes a novel burst-mode clock and data recovery (CDR) circuit which can be used for 622Mbps burst mode applications. The CDR circuit is basically a phase locked loop (PLL) having two phase detectors (PDs), one for the reference clock and the other for the NRZ data, whose operations are controlled by an external control signal. This CDR was fabricated in a 1-poly 5-metal $0.25{\;}\mu\textrm{m}$ CMOS technology. Jitter generation, burst/continuous mode data receptions were tested. Operational frequency range is 320Mhz~720Mhz and BER is less than 1e-12 for PRBS31 at 622Mhz. For the same data sequence, the extracted clock jitter is less than 8ps rms. Power consumption of 100mW was measured without I/O circuits.