• Journal of the Korean Institute of Intelligent Systems
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• v.26 no.4
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• pp.273-278
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• 2016

In this paper, chaotic circuit of the Lorentz system using multipliers, operational amplifiers, capacitor, fixed resistor and variable resistor for control has been designed in a electronic circuit. Through PSPICE program, electrical characteristics such as time waveforms, frequency spectra and phase attractors analyzed. And in the special area ($10{\sim}100k{\Omega}$) of the $500k{\Omega}$ control variable resistor, the circuit showed chaotic dynamics. Also, we implemented the circuit in a electronic hardware system with discrete elements. Measured results of the circuit coincided with simulated data.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.6
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• pp.68-77
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• 2003

An improved negative capacitance circuit that cancels out input impedance of a front-end in a bioimpedance measurement and operates stably with a low gain margin has been proposed. Since the proposed circuit comprises wide-band operational amplifiers, selecting operational amplifiers is easy, while an operational amplifier of prefer bandwidth should be chosen to apply conventional circuit. Also, since gain margin can be controlled by a feedback resistor connected serially with a feedback capacitor, gain margin is tuneable with a potentiometer. The input impedance of the proposed circuit is two times larger than that of the conventional circuit and 40-times than that without a negative capacitance circuit. Furthermore, closed-loop phase response of the proposed circuit is better than that of the conventional circuit or without a negative capacitance circuit. Above all, for the proposed circuit, the frequency at which a gain peaking occurs is higher than the frequency at which the loop gain becomes a maximum. Thus, the proposed circuit is not affected by a gain peaking and can be operated with a very low gain margin.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.10
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• pp.34-39
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• 2016

A low-voltage, low-power analog front-end IC for neural recording implant devices is presented. The proposed IC consists of a low-noise neural amplifier and a programmable active bandpass filter to process neural signals residing in the band of 1 Hz to 5 kHz. The neural amplifier is based on a source-degenerated folded-cascode operational transconductance amplifier (OTA) for good noise performance while the following bandpass filter utilizes a low-power current-mirror based OTA with programmable high-pass cutoff frequencies from 1 Hz to 300 Hz and low-pass cutoff frequencies from 300 Hz to 8 kHz. The total recording analog front-end provides 53.1 dB of voltage gain, $4.68{\mu}Vrms$ of integrated input referred noise within 1 Hz to 10 kHz, and noise efficiency factor of 3.67. The IC is designed using $18-{\mu}m$ CMOS process and consumes a total of $3.2{\mu}W$ at 1-V supply voltage. The layout area of the IC is $0.19 mm^2$.

• Journal of IKEEE
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• v.12 no.3
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• pp.172-175
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• 2008

An improved triangular/square-wave VCO using OTAs is presented. It consists of two OTAs, a timing capacitor, and a resistor. A prototype circuit built with commercially available components exhibits less than 0.01% nonlinearity in its current-to-frequency transfer characteristic from 0.2 to 14 kHz and 450 ppm/$^{\circ}C$ temperature coefficient of frequency over $-20^{\circ}C$ to $40^{\circ}$.

• Journal of Power Electronics
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• v.14 no.1
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• pp.40-47
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• 2014

An average current mode control scheme that consistently offers good dynamic performance for LLC series resonant DC-to-DC converters irrespective of the changes in the operational conditions is presented in this paper. The proposed control scheme employs current feedback from the resonant tank circuit through an integrator-type compensation amplifier to improve the dynamic performance and enhance the noise immunity and reliability of the feedback controller. Design guidelines are provided for both current feedback and voltage feedback compensation. The performance of the new control scheme is demonstrated through an experimental 150 W converter operating with 340 V to 390 V input voltage to provide a 24 V output voltage.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.337-340
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• 2002

This paper describes a phase compensation technique for the low power consumption OTA. Power consumption of the low power OTA is lower than that of the conventional Wang's OTA. However. this circuit has an oscillation problem. The phase margin is -24deg. By using the phase compensation capacitor, the phase margin becomes 52deg. As a result, the low power consumption OTA circuit becomes to have an enough phase margin and to operate stably.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.189-192
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• 2000

In this paper, we propose the novel test method to detect short and open faults in CMOS Op-amp. The proposed method is composed of two test steps - the offset and the high frequency test. Using HSPICE simulation, we get a 100％ fault coverage. To verify the proposed method, we design and fabricate the CMOS op-amp that contains various short and open faults through Hyundai 0.65$\mu\textrm{m}$ 2-poly 2-metal CMOS process. Experimental results of fabricated chip demonstrate that the proposed test method can detect short and open faults in CMOS Op-amp.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.545-548
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• 2004

The paper describes the design of high-speed, high-resolution Sample-and-Hold circuit which shows the conversion rate 80MHz and the power supply of 3.3v with 0.35um CMOS 2-poly 4-metal process for high-speed, high resolution Analog-to-Digital Converter. For improving Dynamic performance of Sample-and-Hold, Two Double bootstrap switch and high performance operational amplifier with gain booster, which are used. and For physical stability of Sample and Hold circuit, reduces excess voltage of gate in bootstrap switch. Simulation results using HSPICE shows the SFDR of 71dB, 75dB in conversion rate of 80MHz result for two inputs(0.5Vpp, 10MHz and 1Vpp, 10MHz) and the power dissipation of 48mW at single 3.3V supply voltage.

• Journal of the Korean Institute of Telematics and Electronics
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• v.20 no.2
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• pp.29-34
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• 1983

A simulated inductance, with a phase parameter control circuit containing only two resistors and one operational amplifier, is realized as a two terminal network. Analytical results of the proposed circuit avow that we can realize a simulated inductance for constant inductance value, and experimental results confirm the theoretical predictions. Error of maximum 4%, between theoretical and experimental results of equivalent inductance, has been observed over a wide range of frequencies up to about 100 KHz.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.507-510
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• 1998

In this paper, a novel test method is proposed to detect hard and soft fault in CMOS operational amplifiers. Proposed test method mark use of the offset character, which is one of the op-amps characteristics. During the test mode, CUT is implemented to unit gain op-amps with feedback loop. When the input is grounded, a good circuit has a small offset voltage, but a faulty circuit has a large offset voltage exceeding predefined range of tolerance. Using the proposed method, no test vector is required to be applied. Therefore the test vector generation problem is eliminated and the test time is reduced. The accuracy and effectiveness of the method is verified through HSPICE simulation.