• 한국수자원학회논문집
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• 제37권6호
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• pp.487-497
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• 2004

하천을 구성하는 수공시스템의 구성요소 중에서 댐과 같이 하천유량 조절에 중요한 역할을 하는 시설이 신규건설을 통해 시스템에 추가되면, 기존 시스템의 운영방식은 이를 고려하여 변화되어야 된다. 기존댐에서 사용되던 운영률은 기왕의 시스템의 입력과 출력에 적합하도록 설계되었으므로, 신규댐이 하천에 추가되면 운영률 또한 이를 고려하여 변화되어야 한다. 본 연구에서는 하천에 신규댐 건설로 인하여 기존댐 운영률의 변화가 필요할 때, 기존댐과 신규댐의 운영목적을 동시에 고려하여 새로운 운영률을 작성하기 위한 기법을 제시하였다. 이를 위하여 추계학적 기법을 통해 발생된 유입량과 최적기법을 사용한 댐 연계운영을 실시하여 저수지 운영률을 개발하였다 본 연구에서 제안된 기법의 검증을 위해 금강유역을 선정해 적용한 결과 새로운 운영률의 적합성을 확인하였다.

• 한국통신학회:학술대회논문집
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• 한국통신학회 1991년도 추계종합학술발표회논문집
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• pp.86-91
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• 1991

A capability of performing the optical logic and arithmetic operations is followed by an effective encoding technique. In this paper, we proposed the color light encoding technique. By using this encoding technique, the space bandwidth product(SBP) is minimized in the output plane. In addition, we proposed the pre-operation pro-carry processing method that performs faster than the same time operation and carry processing method in optical computing. We proposed that the color liquid crystal device(CLCD) is used as the encoded color light input source.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.413-416
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• 1998

This paper presents a dAC calibration technique for high resolution and monolithic operation. The calibration technique consists of basic source, current memory cell (C.M) and current substrator. Current memory supplies the error current to basic source. Current substrator extracts the error current from the main source. It is simple and needs no special calibration period. The proposed current cell has high calibration performance and guarantees 100MHz operation.

• Transactions on Electrical and Electronic Materials
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• 제7권4호
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• pp.180-183
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• 2006

We report for the first time two-bit operational characteristics of a high-density NOR-type polysilicon-oxide-nitride-oxide-silicon (SONOS) array with common source line (CSL). An undesired disturbance, especially drain disturbance, in the NOR array with CSL comes from the two-bit-per-cell operation. To solve this problem, we propose an efficient bulk-biased programming technique. In this technique, a bulk bias is additionally applied to the substrate of memory cell for decreasing the electric field between nitride layer and drain region. The proposed programming technique shows free of drain disturbance characteristics. As a result, we have accomplished reliable two-bit SONOS array by employing the proposed programming technique.

• 전력전자학회논문지
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• 제23권4호
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• pp.240-246
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• 2018

In this paper, a sensorless V/f control based on maximum torque per ampere (MTPA) operation for PMSMs is proposed. Given that the MTPA operation is not considered in the conventional sensorless V/f control, efficient PMSM drives cannot be achieved. Therefore, this paper proposes an improved technique based on the d-axis current control to enable the MTPA operation in the V/f control for PMSMs. A stabilization technique is also proposed to improve the dynamic characteristics and stability against load variation. The effectiveness of the proposed technique is verified by conducting experiments with a 250 W SPMSM for driving a blower.

• Journal of Chest Surgery
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• 제26권5호
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• pp.422-426
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• 1993

We report three cases of children who underwent definitive conversion to the Fontan circulation using a new surgical technique, Extracardiac Epicardial Lateral Tunnel. This new procedure allows the operation to be performed as a totally extracardiac operation [especially in ventricular dysfunction] and allows it to be performed in a very small atrium and in cases with unsuitable pulmonary venous drainage.Our data suggest that this procedure may achieve satisfactory hemodynamics of the total cavopulmonary connection.

• 대한전기학회논문지:시스템및제어부문D
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• 제54권7호
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• pp.458-461
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• 2005

Power dissipated during test application is substantially higher than power dissipated during functional operation which can decrease the reliability and lead to yield loss. This paper presents a new technique for power minimization during test application in full scan sequential circuits. This paper shows freezing of combinational logic parts during scan shift operation in test mode. The freezing technique leads to power to minimization. Significant power reduction in the scan techniques is achieved on ISCAS 89 benchmarks.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 제39회 하계학술대회
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• pp.1963-1964
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• 2008

Scan design is a structured design-for-testability technique in which flip-flops are re-designed so that the flip-flops are chained in shift registers. We propose a new technique to re-design about clock operation. This technique propose about low power operation of scan clock and saved time of test operation.

• 전기학회논문지
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• 제58권9호
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• pp.1706-1713
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• 2009

In this paper, a parallel operation algorithm for high power PEMFC generation systems is proposed. According to increasing the capacity of fuel cell systems with several fuel cell stacks, the different dynamic characteristics of each fuel cell stack effect on imbalance of load sharing and current distribution, so that a robust parallel operation algorithm is desired. Therefore, a power-sharing technique is developed and explained in order to design an optimal distributed PEMFC generation system. In addition, an optimal controller design procedure for the proposed parallel operation algorithm is introduced, along with informative simulations and experimental results.

• Journal of Information Processing Systems
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• 제9권3호
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• pp.499-510
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• 2013

Hardware-Software co-simulation of a multiple image encryption technique shall be described in this paper. Our proposed multiple image encryption technique is based on the Latin Square Image Cipher (LSIC). First, a carrier image that is based on the Latin Square is generated by using 256-bits of length key. The XOR operation is applied between an input image and the Latin Square Image to generate an encrypted image. Then, the XOR operation is applied between the encrypted image and the second input image to encrypt the second image. This process is continues until the nth input image is encrypted. We achieved hardware co-simulation of the proposed multiple image encryption technique by using the Xilinx System Generator (XSG). This encryption technique is modeled using Simulink and XSG Block set and synthesized onto Virtex 2 pro FPGA device. We validated our proposed technique by using the hardware software co-simulation method.