• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.12
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• pp.2675-2680
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• 2010

Computation steps for 3D graphic processing consist of two stages - fixed operation stage and programming required stage. Using this characteristic of 3D pipeline, a hybrid structure between graphics hardware designed by fixed structure and programmable hardware based on instructions, can handle graphic processing more efficiently. In this paper, fragment Shader is designed under this hybrid structure. It also supports OpenGL ES 2.0. Interior interface is optimized to reduce the delay of entire pipeline, which may be occurred by data I/O between the fixed hardware and the Shader. Interior register group of the Shader is designed by an interleaved structure to improve the register space and processing speed.

• Journal of the Korea Computer Graphics Society
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• v.11 no.2
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• pp.56-63
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• 2005

모바일 환경에서 고급 그래픽스 기술을 적용하고자 하는 시도로 최근 3D 그래픽 엔진을 탑재한 단말기가 출시되고 있다. 이 단말기는 OpenGL ES 1.x 을 기준으로 고정된 파이프라인을 통해 그래픽 연산을 처리하고 있으므로 사용자가 다양한 그래픽 표현을 수행하는데 제약이 따른다. 최근 PC 환경의 그래픽 엔진에서는 고정 기능의 파이프라인이 아닌 프로그래밍 가능한 파이프라인을 제공하여 기존 고정 파이프라인에서 불가능했던 유연한 그래픽스 기술을 제공하고 있다. PC환경의 프로그래밍 가능한 파이프라인은 DirectX 와 OpenGL ARB Extension 그래픽 라이브러리에 의해 제공되고 있지만, 모바일 환경에서는 이를 지원하기 위한 관련 제품이 아직 출시되지 않고 있는 상태이다. 본 논문에서는 OpenGL ARB Extension 1.0 을 근거로 정점 프로세싱 과정을 프로그래밍 가능한 파이프라인 구조로 동작하도록 하는 모바일용 정점 프로그램 가상머신을 제시한다.

• Journal of IKEEE
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• v.13 no.2
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• pp.253-259
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• 2009

In this paper, we propose a novel architecture of a general graphics shader processor without a dedicated hardware. Recently, mobile devices require the high performance graphics processor as well as the small size, low power. The proposed shader processor is a GP-GPU(General-Purpose computing on Graphics Processing Units) to execute the whole OpenGL ES 2.0 graphics pipeline by using shader instructions. It does not require the separate dedicate H/W such as rasterization on this fully programmable capability. The fully programmable 3D graphics shader processor can reduce much of the graphics hardware. The chip size of the designed shader processor is reduced 60% less than the sizes of previous processors.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.3
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• pp.547-554
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• 2008

In this paper, two-stage pipelined floating-point multiplier (FP-MUL) is designed. The FP-MUL processor supports single precision multiplication for 3D graphic APIs, such as OpenGL and Direct3D and has area-efficient and low-latency architecture via saturated arithmetic, area-efficient sticky-bit generator, and flagged prefix adder. The FP-MUL has about 4-ns delay time under $0.13{\mu}m$ CMOS standard cell library and consists of about 7,500 gates. Because its maximum performance is about 250 MFLOPS, it can be applicable to mobile 3D graphics application.

• Journal of information and communication convergence engineering
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• v.6 no.3
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• pp.285-288
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• 2008

Most of multimedia processors for 2D/3D graphics acceleration use a lot of integer/floating point arithmetic units. We present a new architecture with an efficient ALU, built in a smaller chip size. It reduces instruction cycles significantly based on a foundation of multi-thread operation, variable length instruction words, dual phase operation, and phase instruction's coordination. We can decrease the number of instruction cycles up to 50%, and can achieve twice better performance.

• Korean Journal of Remote Sensing
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• v.28 no.2
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• pp.245-253
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• 2012

The public and civilian demands regarding 3D geo-spatial information processing on mobile device including smartphone are increasing. But there are few actual implementations or application cases. This work is to present some results by a prototype implementation of 3D terrain information visualization function with satellite image and DEM using HTML5 WebGL, which is a web-based graphic library under the standardization process. This is a useful standard for cross-platform operation for 3D graphic rendering without other plug-in modules. As the results, in the different types of operating system or browser in a personal computer or a smartphone, it shows same rendering results, as long as they support HTML5 WebGL. As well;geo-metadata search and identification functions for data sets for 3D terrain visualization process are added in this implementation for the practical aspect.

• Journal of the Korea Computer Graphics Society
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• v.28 no.2
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• pp.21-28
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• 2022

ASTC is one of the standard texture formats supported in OpenGL ES 3.2 and Vulkan 1.0 (and later versions), and it has been increasingly used on mobile platforms (Android and iOS). ASTC's most important feature is the block size configuration, thereby providing a trade-off between compression quality and rates. With the higher number of textures, however, it is difficult to manually determine the optimal block sizes of each texture. To solve the problem, we present a new approach based on PSNR values to automatically determine the ASTC block size. A brute-force approach, which compresses a texture on all block sizes and compares the PSNR values of the compressed textures, can increase the compression time by up to 14 times. In contrast, our three-step approach minimizes the compression-time overhead. According to our experiments on a texture set including 64 various textures, our method determined the block sizes from 4×4 to 12×12 and reduced the size of compressed files by 68%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.2 s.344
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• pp.24-33
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• 2006

The effective geometry processing IP architecture for mobile SoC that has real time 3D graphics acceleration performance in mobile information system is proposed. Base on the proposed IP architecture, we design the floating point arithmetic unit needed in geometry process and the floating point geometry processor supporting the 3D graphic international standard OpenGL-ES. The geometry processor is implemented by 160k gate area in a Xilinx-Vertex FPGA and we measure the performance of geometry processor using the actual 3D graphic data at 80MHz frequency environment The experiment result shows 1.5M polygons/sec processing performance. The power consumption is measured to 83.6mW at Hynix 0.25um CMOS@50MHz.

• Journal of IKEEE
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• v.11 no.4
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• pp.358-363
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• 2007

This paper presents a floating point unit(FPU) with 3 stages for a 3D graphics shader engine. It targeted to accelerate 3D graphics in portable device environments. In order to design a balanced architecture for a shader engine, we analyzed shader assembly instructions and estimated the performance of FPU with the method we propose. The proposed unit handles 4-dimensional data through separated two paths that are lead to general operation module and special function module. The proposed FPU is compiled as a form of the cascade FPU with 3 stages to efficiently handle a matrix operation with relatively low hardware overhead. Except some complex instructions that are executed using macro instructions, all instructions complete an operation in a single instruction cycle at 100MHz frequency. A special function module performs all operations in a single clock cycle using the Newton Raphson method with the look-up table.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2012.11a
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• pp.17-18
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• 2012

본 논문에서는 스마트폰에서 해당 기기에 장착된 카메라로부터 실시간으로 입력되는 프리뷰 영상에 대하여 실시간으로 영상처리를 수행할 수 있는 프레임워크를 제안한다. 본 논문에서 제안하는 프레임워크의 경우 OpenGL ES 2.0 기반의 Shading Language 를 이용하여 모바일 GPU 에서 병렬처리를 수행함으로써 영상처리 알고리즘을 고속으로 적용할 수 있으며, 매 프레임의 입력 영상을 텍스처로 지정하고 연산 결과가 저장된 프레임 버퍼의 내용을 그대로 화면에 출력함으로써 메인 메모리와 GPU 메모리 사이의 자료 이동을 최소화 하였다. 현재 상용화 된 스마트폰에 제안하는 프레임워크를 이용하여 적용시킨 결과 필터링 기반의 여러 가지 영상처리 알고리즘의 실시간 처리가 가능함을 보여줌으로써 본 논문에서 제안하는 프레임워크의 실시간 활용을 확인할 수 있다.