• Proceedings of the KIEE Conference
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• 1985.07a
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• pp.282-283
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• 1985

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.717-722
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• 2004

A design was done, and all characteristic of photodetectr of the web pattern type which a standard process of the Bipolar which Si PIN structure was used in this paper, and was used for the current amplifier design was used, and high-speed, was used as receiving optcal area of high altitude, and the module which had a low dark current characteristic was implemented with one chip with a base. Important area decreases an area of Ie at the time of this in order to consider an electrical characteristic and economy than the existing receiving IC, and performance of a product and confidence are got done in incense. First of all, the receiving IC which a spec, pattern of a wafer to he satisfied with the following electrical optical characteristic that produced receiving IC of 5V and structure are determined, and did one-chip is made. On the other hand, the time when AR layer of double is $Si_{3}N_{4}/SiO_{2}=1500/1800$ has an optical reflectivity of less than $10{\%}$ on an incidence optical wavelength of 660 ,and, in case of photo detector which reverse voltage made with 1.8V runs in 1.65V, an error about a change of thickness is very the thickness that can be improved surely. And, as for the optical current characteristic, about 5 times increases had the optical current with 274nA in 55nA when Pc was -27dBm. A BJT process is used, and receiving IC running electricity suitable for low voltage and an optical characteristic in minimum 1.8V with a base with two phases is made with one chip. IC of low voltage operates in 1.8V and 3.0V at the same time, and optical link receiving IC is going to be implemented

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.152-159
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• 2004

In this study, we design the one-chip PWM IC with high voltage power switch (300V class LDMOSFET) for SMPS (Switching Mode Power Supply) application. Reference circuits generate constant voltage(5V) in the various of power supply and temperature condition. Error amp. is designed with large DC gain $({\simeq}65dB)$, unity frequency $({\simeq}190kHz)$ and large $PM(75^{\circ})$. comparator is designed with 2 stage. Saw tooth generators operate with 20kHz oscillation frequency. Also, we optimize drift concentration & drift length of n-LDMOSFET for design of high voltage switching device. It is shown that simulation results have the breakdown voltage of 350V. (using ISE-TCAD Simulation tool). PWM IC with power switching device is designed with 2um design rule and Bi-DMOS technology.

• Journal of Power Electronics
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• v.16 no.3
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• pp.1209-1217
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• 2016

This paper presents a novel charge pump scheme that combines the advantages of Fibonacci and Dickson charge pumps to obtain 30 V voltage for display driver integrated circuit application. This design only requires four external capacitors, which is suitable for a small-package application, such as smart card displays. High-amplitude (<6.6 V) clocks are produced to enhance the gate drive of a Dickson charge pump and improve the system's current drivability by using a voltage-doubler charge pump with a pulse skip regulator. This regulation engages many middle-voltage devices, and approximately 30% of chip size is saved. Further optimization of flying capacitors tends to decrease the total chip size by 2.1%. A precise and simple model for a one-stage Fibonacci charge pump with current load is also proposed for further efficiency optimization. In a practical design, its voltage error is within 0.12% for 1 mA of current load, and it maintains a 2.83% error even for 10 mA of current load. This charge pump is fabricated through a 0.11 μm 1.5 V/6 V/32 V process, and two regulators, namely, a pulse skip one and a linear one, are operated to maintain the output of the charge pump at 30 V. The performances of the two regulators in terms of ripple, efficiency, line regulation, and load regulation are investigated.

• The KIPS Transactions:PartC
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• v.19C no.1
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• pp.39-46
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• 2012

In this paper, we propose a key distribution scheme for flexible chipset pairing conditional access system. Chipset pairing conditional access system is the implementation of CA (Conditional Access) module by using both embedded secure chip in a Set-Top Box(STB) and smartcard, and the secure chip embedded in a STB forms a secure channel between the smartcard and the STB. In short, it is the system that a smartcard outputs encrypted CW (Control Word) to the STB, and the STB decrypts an encrypted CW by using the embedded secure chip. The drawback of this chipset pairing conditional access system is that one smartcard is able to be used for only one specified STB since it is the system using the STB bound to a smartcard. However, the key distribution scheme proposed in this paper overcomes a drawback of current chipset pairing conditional access system by using Chinese Remainder Theorem(CRT). To be specific, with this scheme, one smartcard can be used for multiple, not single, STBs, and applied to current chipset pairing without great changes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.10
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• pp.17-23
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• 2003

In this study, microscale, high-performance, solenoid-type RF chip inductors were investigated. The size of the RF chip inductors fabricated in this work was 1.0${\times}$0.5${\times}$0.5㎣. The materials (96% Al2O3) and shape (I-type) of the core were determined by a Maxwell three-dimensional field simulator to maximize the performance of the inductors. The copper (Cu) wire with 40${\mu}{\textrm}{m}$ diameter was used as the coils. High frequency characteristics of the inductance (L), quality-factor (Q), and capacitance (C) of developed inductors were measured using an RF Impedance/Material Analyzer (HP4291B with HP16193A test fixture). The inductors developed have inductances of 11 to 39 nH and quality factors of 28 to 50 over the frequency ranges of 250MHz to 1 GHz, and show results comparable to those measured for the inductors prepared by CoilCraf $t^{Tm}$ that is one of the best chip inductor company in the world. The simulated data predicted the high-frequency data of the L, Q, and C of the inductors developed well.l.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.1
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• pp.41-45
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• 2018

As the size of semiconductor chip shrinks, the electronic industry has been paying close attention to fan-out wafer level packaging (FO-WLP) as an emerging solution to accommodate high input and output density. FO-WLP also has several advantages, such as thin thickness and good thermal resistance, compared to conventional packaging technologies. However, one major challenge in current FO-WLP manufacturing process is to control wafer warpage, caused by the difference of coefficient of thermal expansion and Young's modulus among the materials. Wafer warpage induces misalignment of chips and interconnects, which eventually reduces product quality and reliability in high volume manufacturing. In order to control wafer warpage, it is necessary to understand the effect of material properties and design parameters, such as chip size, chip to mold ratio, and carrier thickness, during packaging processes. This paper focuses on the effects of thickness of chip and molding compound on 12" wafer warpage after PMC of EMC using finite element analysis. As a result, the largest warpage was observed at specific thickness ratio of chip and EMC.

• Journal of Sensor Science and Technology
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• v.29 no.2
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• pp.128-132
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• 2020

Total organic carbon (TOC) analysis equipment, which was previously used to prevent eutrophication in advance, is heavy, bulky, and expensive; therefore, so it is difficult to be carried and has been used as an experimental unit. In this study, a through-carbon analysis chip that integrates pretreatment through photocatalytic oxidation and carbon dioxide measurement using a pH indicator was investigated. Both the total carbon - inorganic carbon method and the nonpurgeable organic carbon (NPOC) measurement method require an acidification part for injecting an acid solution for inorganic carbon measurement and removal, an oxidation part for total carbon or NPOC oxidation and a measurement part for Carbon dioxide (CO₂) measurement. Among them, the measurement of oxidation and CO₂ requires physical technology. The proposed TOC analysis chip decomposed into CO₂ as a result of the oxidizing of organic carbon using a photocatalyst, and the pH indicator that was changed by the generated CO₂ was optically measured. Although the area of the sample of the oxidation part and the pH indicator of the measurement part were distinguished in an enclosed space, CO₂ was quantified by producing an oxidation part and a measurement part that shared the same air in one chip. The proposed TOC analysis chip is less expensive and smaller, cost and size are disadvantages of existing organic carbon analysis equipment, because it does not require a separate carrier gas to transport the CO₂ gas in the oxidation part to the measurement part.

• Journal of Welding and Joining
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• v.24 no.2
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• pp.64-70
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• 2006

The 3-dimensional (3D) chip stacking technology is a leading technology to realize a high density and high performance system in package (SiP). There are several kinds of methods for chip stacking, but the stacking and interconnection through Cu filled through-hole via is considered to be one of the most advanced stacking technologies. Therefore, we studied the optimum process of through-hole via formation and Cu filling process for Si wafer stacking. Through-hole via was formed with DRIE (Deep Reactive ion Etching) and Cu filling was realized with the electroplating method. The optimized conditions for the via formation were RE coil power of 200 W, etch/passivation cycle time of 6.5 : 6 s and SF6 : C4F8 gas flow rate of 260 : 100 sccm. The reverse pulsed current of 1.5 A/dm2 was the most favorable condition for the Cu electroplating in the via. The Cu filled Si wafer was chemically and mechanically polished (CMP) for the following flip chip bumping technology.