• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.2
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• pp.128-133
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• 2008

Phase-change random access memory (PRAM) chip cell phase of amorphous state is rapidly changed to crystal state above 160 Celsius degree within several seconds during Infrared (IR) reflow. Thus, on-board programming method is considered for PRAM chip programming. We demonstrated the functional 512Mb PRAM with 90nm technology using several novel core circuits, such as metal-2 line based global row decoding scheme, PN-diode cells based BL discharge (BLDIS) scheme, and PMOS switch based column decoding scheme. The reverse-state standby current of each PRAM cell is near 10 pA range. The total leak current of 512Mb PRAM chip in standby mode on discharging state can be more than 5 mA. Thus in the proposed BLDIS control, all bitlines (BLs) are in floating state in standby mode, then in active mode, the activated BLs are discharged to low level in the early timing of the active period by the short pulse BLDIS control timing operation. In the conventional sense amplifier, the simultaneous switching activation timing operation invokes the large coupling noise between the VSAREF node and the inner amplification nodes of the sense amplifiers. The coupling noise at VSAREF degrades the sensing voltage margin of the conventional sense amplifier. The merit of the proposed sense amplifier is almost removing the coupling noise at VSAREF from sharing with other sense amplifiers.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.2
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• pp.28-34
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• 2011

In this paper, we present integer and fractional motion estimation IP for H.264/AVC encoder by hardware-oriented algorithm. In integer motion engine, the reference block is used to share for consecutive current macro blocks in parallel processing which exploits data reusability and reduces off-chip bandwidth. In fractional motion engine, instead of two-step sequential refinement, half and quarter pel are processed in parallel manner in order to discard unnecessary candidate positions and double throughput. The H.264/AVC motion estimation chip is fabricated on a MPW(Multi-Project Wafer) chip using the chartered $0.18{\mu}m$ standard CMOS 1P5M technology and achieves high throughput supporting HDTV 720p 30 fps.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.2
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• pp.43-51
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• 2014

In 3-dimensional (3D) integrated package, thermal management is one of the critical issues due to the high heat flux generated by stacked multi-functional chips in miniature packages. In this study, we used numerical simulation method to analyze the thermal behaviors, and investigated the thermal issues of 3D package using TSV (through-silicon-via) technology for mobile application. The 3D integrated package consists of up to 8 TSV memory chips and one logic chip with a interposer which has regularly embedded TSVs. Thermal performances and characteristics of glass and silicon interposers were compared. Thermal characteristics of logic and memory chips are also investigated. The effects of numbers of the stacked chip, size of the interposer and TSV via on the thermal behavior of 3D package were investigated. Numerical analysis of the junction temperature, thermal resistance, and heat flux for 3D TSV package was performed under normal operating and high performance operation conditions, respectively. Based on the simulation results, we proposed an effective integration scheme of the memory and logic chips to minimize the temperature rise of the package. The results will be useful of design optimization and provide a thermal design guideline for reliable and high performance 3D TSV package.

• Electrical & Electronic Materials
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• v.10 no.4
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• pp.349-354
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• 1997

This paper aims at studying the improvement of test method for t-weight sensitive fault (t-wsf) detect. The development of RAM fabrication technology results in not only the increase at device density on chips but also the decrease in line widths in VLSI. But, the chip size that was large and complex is shortened and simplified while the cost of chips remains at the present level, in many cases, even lowering. First of all, The testing patterns for RAM fault detect, which is apt to be complicated , need to be simplified. This new testing method made use of Local Lower Bound (L.L.B) which has the memory with the beginning pattern of 0(l) and the finishing pattern of 0(1). The proposed testing patterns can detect all of RAM faults which contain stuck-at faults, coupling faults. The number of operation is 6N at 1-weight sensitive fault, 9,5N at 2-weight sensitive fault, 7N at 3-weight sensitive fault, and 3N at 4-weight sensitive fault. This test techniques can reduce the number of test pattern in memory cells, saving much more time in test, This testing patterns can detect all static weight sensitive faults and pattern sensitive faults in RAM.

• Journal of the Korea Society of Computer and Information
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• v.11 no.2 s.40
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• pp.35-42
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• 2006

In this paper we implement a new simulator for performance analysis of a parallel digital signal processing distributed shared memory multiprocessor systems. using Parsec The key idea of this simulator is suitable in simulation of system that uses DMA function of TMS320C6701 DSP chip and local memory which have fast access time. Also, because correction of performance parameter and reconfiguration for hardware components are easy, we can analyze performance of system in various execution environments. In the simulation, FET, 2D FET, Matrix Multiplication. and Fir Filter, which are widely used DSP algorithms. have been employed. Using our simulator, the result has been recorded according to different the number of processor, data sizes, and a change of hardware element. The performance of our simulator has been verified by comparing those recorded results.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.386-389
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• 2013

In this paper, for signal integrity analysing high-speed signal between a processor and a DDR2 memory, transient analysis is done and eye diagrams are generated using IBIS models of IC chips and S-parameters of transmission line. From the eye diagrams of such high-speed signals as DQ, DQS/DQSb, Clock, Address and Control, signal quality is assured through measuring timing and voltage margins during setup and hold times and verifying that the over-/under-shoot and the cross points of differential signals satisfy their specifications.

• Journal of the Microelectronics and Packaging Society
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• v.7 no.1
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• pp.19-24
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• 2000

To make stacked chip packages far high-density packaging of memory chips used in workstations or PC severs, several lead-frames are to be connected vertically. Fer this purpose. Sn or Sn/Ag were electrochemically deposited on Cu lead-frames and their microstructures were examined by XRD and SEM. Then, two specimens were annealed at $250^{\circ}C$ for 10 min. and pressed to be joined. The shear stresses of joined lead-frames were measured fur comparison. In the case of Sn only, $Cu_3Sn$ was formed by the reaction of Sn and Cu lead-frames. In the case of Sn/Ag, besides $Cu_3Sn$. $Ag_3Sn$ was formed by the reaction of Sn and Ag. Compared to joined specimens made from Sn only, those made from Sn/Ag showed 1.2 times higher shear stress. This was attributed to the $Ag_3Sn$ phase formed at the joined interface.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.1
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• pp.1-6
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• 2021

The paper proposes the design of AES-based encryption chip for IoT security. ROM based S-Box implementation occurs a number of memory space and some delay problems for its access. In this approach, S-Box is designed by pipeline structure on composite field GF((22)2) to get faster calculation results. In addition, in order to achieve both higher throughput and less delay, shared S-Box are used in each round transformation and the key scheduling process. The proposed AES crypto-processor is described in Veilog-HDL, and Xilinx ISE 14.7 tool is used for logic synthesis by using Xilinx XC6VLX75T FPGA. In order to perform the verification of the crypto-processor, the timing simulator(ModelSim 10.3) is also used.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.3
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• pp.355-366
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• 2022

This paper proposes a microcode-based neural network accelerator controller for artificial intelligence accelerators that can be reconstructed using a programmable architecture and provide the advantages of low-power and ultra-small chip size. In order for the target accelerator to support various neural network models, the neural network model can be converted into microcode through microcode compiler and mounted on accelerator to control the operators of the accelerator such as datapath and memory access. While the proposed controller and accelerator can run various CNN models, in this paper, we tested them using the YOLOv2-Tiny CNN model. Using a system clock of 200 MHz, the Controller and accelerator achieved an inference time of 137.9 ms/image for VOC 2012 dataset to detect object, 99.5ms/image for mask detection dataset to detect wearing mask. When implementing an accelerator equipped with the proposed controller as a silicon chip, the gate count is 618,388, which corresponds to 65.5% reduction in chip area compared with an accelerator employing a CPU-based controller (RISC-V).

• The KIPS Transactions:PartA
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• v.14A no.5
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• pp.301-308
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• 2007

This paper proposes high performance coprocessor architecture for real time dense disparity computation based on a phase-based binocular stereo matching technique called local weighted phase-correlation(LWPC). The algorithm combines the robustness of wavelet based phase difference methods and the basic control strategy of phase correlation methods, which consists of 4 stages. For parallel and efficient hardware implementation, the proposed architecture employs SIMD(Single Instruction Multiple Data Stream) architecture for each functional stage and all stages work on pipelined mode. Such that the newly devised pipelined linear array processor is optimized for the case of row-column image processing eliminating the need for transposed memory while preserving generality and high throughput. The proposed architecture is implemented with Xilinx HDL tool and the required hardware resources are calculated in terms of look up tables, flip flops, slices, and the amount of memory. The result shows the possibility that the proposed architecture can be integrated into one chip while maintaining the processing speed at video rate.