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A Low Memory Bandwidth Motion Estimation Core for H.264/AVC Encoder Based on Parallel Current MB Processing  

Kim, Shi-Hye (Kyungpook National University, School of Electrical Engineering and Computer Science)
Choi, Jun-Rim (Kyungpook National University, School of Electrical Engineering and Computer Science)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.48, no.2, 2011 , pp. 28-34 More about this Journal
Abstract
In this paper, we present integer and fractional motion estimation IP for H.264/AVC encoder by hardware-oriented algorithm. In integer motion engine, the reference block is used to share for consecutive current macro blocks in parallel processing which exploits data reusability and reduces off-chip bandwidth. In fractional motion engine, instead of two-step sequential refinement, half and quarter pel are processed in parallel manner in order to discard unnecessary candidate positions and double throughput. The H.264/AVC motion estimation chip is fabricated on a MPW(Multi-Project Wafer) chip using the chartered $0.18{\mu}m$ standard CMOS 1P5M technology and achieves high throughput supporting HDTV 720p 30 fps.
Keywords
H.264/AVC Encoder; Integer Motion Estimation; Parallel processing;
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