1 |
Y. J. Wang, C. C. Cheng, and T. S. Chang, "A fast algorithm and its VLSI architecture for fractional motion estimation for H.264/MPEG-4 AVC coding," IEEE Trans. Circuits Syst. Video Technol., vol. 17, no. 5, pp. 578-583, May. 2007.
DOI
|
2 |
JVT H.264/AVC Reference Software JM 12.2.
|
3 |
J. S. Youn, J. R. Choi, and S. S. Han, "Parallel integer motion estimation method by using reference blocks shared for HD video coding," 2009 International Conference on Electronic Computer Technology, pp. 577-581, Feb. 2009.
|
4 |
S. Y. Yap and J. V. McCanny, "A VLSI architecture for variable block size video motion estimation," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 51, no. 7, pp. 384-389, Jul. 2004.
DOI
|
5 |
M. Kim, I. Hwang, and S. I. Chae, "A fast vlsi architecture for full search variable block size motion estimation in MPEG-4 AVC/H.264," in Proc. Asia South Pacific Design Autom. Conf., vol. 1, pp. 631-634, Jan. 2005..
|
6 |
C. L. Su, W. S. Wang, U. L. Chen, Y. C. Wang, C. W. Chen, J. I. Guo, and S. Y. Tseng, "A low complexity high quality integer motion estimation architecture design for H.264/AVC," in Proc IEEE Asia Pacific Conf. Circuits Syst., pp. 398-401, Dec. 2006.
|
7 |
J. Ostermann, J. Bormans, P. List, D. Marpe, M. Narroschke, F. Pereira, T. Stockhammer, and T. Wedi, "Video coding with H.264/AVC: tools, performance, and complexity," IEEE Circuits Syst. Mag., vol. 4, no. 1, pp. 7-28, First Quarter, 2004.
DOI
ScienceOn
|
8 |
T. C. Chen, Y. W. Huang, and L. G. Chen, "Fully utilized and reusable architecture for fractional motion estimation of H.264/AVC," ICASSP, vol. 5, pp. 9-12, May. 2004.
|
9 |
J. C. Tuan, T. S. Chang, and C. W. Jen, "On the data reuse and memory bandwidth analysis for full-search block-matching VLSI architecture," IEEE Trans. Circuits Syst. Video Technol., vol. 12, no. 1, pp. 61-72, Jan. 2002.
DOI
ScienceOn
|
10 |
T. C. Chen, S. Y. Chien, Y. W. Huang, C. H. Tsai, C. Y. Chen, Y. W. Chen, and L. G. Chen, "Analysis and architecture design of an HDTV. 720p 30frames/s H.264/AVC encoder," IEEE Trans. Circuits Syst. Video Technol., vol.16, no.6, pp.677-679, June 2006.
|
11 |
D. X. Li, W. Zheng, and M. Zhang, "Architecture design for H.264/AVC integer motion estimation with minimum memory bandwidth," IEEE Trans. Consumer Electron., vol. 53, no. 3, pp. 1053-1060, Aug. 2007.
DOI
|
12 |
Z. Liu, Y. Song, M. Shao, S. Li, L. Li, S. Ishiwata, M. Nakagawa, S. Goto, and T. Ikenaga, "HDTV 1080p H.264/AVC encoder chip design and performance analysis," IEEE Jounal of Solid-State Circuits, vol. 44, no. 2, pp. 594-606, Feb. 2009.
DOI
|