• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.1
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• pp.64-72
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• 1993

We propose "algorithm MA" which can detect PSF that is the functional fault in RAM. This algorithm based on the restricted PSF(or neighborhood PSF) and can detect not only conventional stuck-at and transition faults but also SNPSF, PNPSF and partially ANPSF. The time complexity of "algorithm MA" has 1536xP(P=no. of partition). We propose total BIST(built-in self test) scheme which implement this algorithm in memory chip.ithm in memory chip.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.4
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• pp.91-95
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• 2017

Package-On-Package (PoP) technology is developing toward smaller form factors with high-speed data transfer capabilities to cope with high DDR4x memory capacity. The common application processor (AP) used for PoP devices in smartphones has the bottom package as logic and the top package as memory, which requires both thermally and electrically enhanced functions. Therefore, it is imperative that PoP designs consider both thermal and power distribution network (PDN) issues. Stacked packages have poorer thermal dissipation than single packages. Since the bottom package usually has higher power consumption than the top package, the bottom package impacts the thermal budget of the top package (memory). This paper investigates the thermal and electrical characteristics of PoP designs, particularly the bottom package. Findings include that via and dense via-cluster volume have an important role to lower thermal resistance to the motherboard, which can be an effective way to manage chip hot spots and reduce the thermal impact on the memory package. A Cu block and dense via-cluster layout with an optimal location are proposed to drain the heat from the chip hot spots to motherboard which will enhance thermal and electrical performance at the design stage. The analytical thermal results can be used for design guidelines in 3D packaging.

• Proceedings of the Materials Research Society of Korea Conference
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• 1995.11a
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• pp.3-3
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• 1995

Plastic IC encapsulation utilizing lead on chip(LOC) die attach technique allows higher device density per unit package area, and faster current speed and easter leadframe design. Nevertheless, since the top surface of the chip is directly attached to the area of the leadframe with a double-sided adhesive tape in the LOC package, it tends to be easily damaged by the leadframe, leading to limitation in its utilization. In this work, it is detailed how the damage of the chip surface occurs, and it is influenced and improved by the LOC construct.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.24 no.1
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• pp.97-101
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• 2024

In this paper, we present the implementation of proton beam irradiation test logic and test results for Xilinx's RFSoC FPGA. In addition to the FPGA function, RFSoC is a chip that integrates CPU, ADC, and DAC and is attracting attention in the defense and space industries aimed at reducing the size of the chip. In order to use these chips in a space environment, an analysis of radiation effects was required and radiation mitigation measures were required. Through the proton irradiation test, the logic to measure the radiation effect of RFSoC was designed. Logic for comparing values stored in memory with normal values was implemented, and protons were irradiated to RFSoC to measure SEU generated in the block memory area. To alleviate the occurrence of SEU in other areas, TMR and SEM were applied and designed. Through the test results, we intend to verify this test configuration and establish an environment in which logic design for satellites can be verified in the future.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.9
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• pp.237-243
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• 2012

In recent system-on-chip (SoC) designs, several hundred embedded memory cores have occupied the largest portion of the chip area. Therefore, the yield of SoCs is strongly dependent on the yield of the embedded memory cores. If all memories had built-in self repair (BISR) with optimal repair rates, the area overhead would be very large. A bit-map sharing method using a memory grouping is proposed to reduce the area overhead. Since the bit-map memory occupies the largest portion of the area of the built-in redundancy analysis (BIRA), the proposed bit-map sharing method can greatly reduce the area overhead of the BIRA. Based on the experimental results, the proposed method can reduce the area overhead by about 80%.

• IEIE Transactions on Smart Processing and Computing
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• v.2 no.4
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• pp.226-239
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• 2013

A number of systems have several on-chip memories with cache memory being one of them. Conventional cache memory consists of SRAM but the ratio of static energy to the total energy of the memory architecture becomes larger as the leakage power of traditional SRAM increases. Spin-Torque Transfer RAM (STT-RAM), which is a variety of Non-Volatile Memory (NVM), has many advantages over SRAM, such as high density, low leakage power, and non-volatility, but it consumes too much writing energy. This study evaluated a wide range of energy consumptions of a two-level cache using NVM partially on a mobile processor. Through a number of experimental evaluations, it was confirmed that the use of NVM partially in the two-level cache effectively reduces energy consumption significantly.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.11C
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• pp.1102-1110
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• 2007

In this paper, we design the FPGA (Field-Programmable Gate Array) of the CAMB (Constant-Amplitude Multi-code Biorthogonal) modulation, and implement the SoC (System on Chip). The ASIC (Application Specific Integrated Circuit) chip is be implemented through targeting and board test. This 12Mbps modem SoC includes the ARM (Advanced RISC Machine)7TDMI, 64Kbyte SRAM(Static Random Access Memory) and ADC (Analog to Digital Converter)/DAC (Digital to Analog Converter) for flexible applications. Additionally, the modem SoC can support the variable communication interfaces such as the 16-bits PCMCIA (Personal Computer Memory Card International Association), USB (Universal Serial Bus) 1.1, and 16C550 Compatible UART (Universal Asynchronous Receiver/Transmitter).

• ETRI Journal
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• v.28 no.4
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• pp.525-528
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• 2006

In this letter, we present a design of a single chip video decoder called advanced mobile video ASIC (A-MoVa) for mobile multimedia applications. This chip uses a mixed hardware/software architecture to improve both its performance and its flexibility. We designed the chip using a partition between the hardware and software blocks, and developed the architecture of an H.264 decoder based on the system-on-a-chip (SoC) platform. This chip contains 290,000 logic gates, 670,000 memory gates, and its size is $7.5\;mm{\times}7.5\;mm$ (using 0.25 micron 4-layers metal CMOS technology).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.1
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• pp.72-79
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• 2003

Due to the improvements in circuit design technique and manufacturing technique, complexity of a circuit is growing along with the demand for memories with large capacities. Likewise, as a memory capacity gets larger, testing gets harder and testing cost increases, and testing process in chip development gets larger as well. Therefore, a research on an effective test algorithm to improve the chip yield rate in a short time period is becoming an important task. This paper proposes an effective, March C-algorithm based, test algorithm that can also be applied to a dual-port memory since it considers all the fault types, which can be occurred in a single-port as well as in a dual-port memory, without increasing the test length.

• Journal of Computing Science and Engineering
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• v.9 no.2
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• pp.51-72
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• 2015

Time predictability is crucial in hard real-time and safety-critical systems. Cache memories, while useful for improving the average-case memory performance, are not time predictable, especially when they are shared in multicore processors. To achieve time predictability while minimizing the impact on performance, this paper explores several time-predictable scratch-pad memory (SPM) based architectures for multicore processors. To support these architectures, we propose the dynamic memory objects allocation based partition, the static allocation based partition, and the static allocation based priority L2 SPM strategy to retain the characteristic of time predictability while attempting to maximize the performance and energy efficiency. The SPM based multicore architectural design and the related allocation methods thus form a comprehensive solution to hard real-time multicore based computing. Our experimental results indicate the strengths and weaknesses of each proposed architecture and the allocation method, which offers interesting on-chip memory design options to enable multicore platforms for hard real-time systems.