• Journal of KIISE:Computer Systems and Theory
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• v.32 no.11_12
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• pp.587-597
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• 2005

Flash memory based embedded computing systems are becoming increasingly prevalent.These systems typically have to provide an instant start-up time. However, we observe that mounting a file system toy flash memory takes 1 to 25 seconds mainly depending on the flash capacity. Since the flash chip capacity is doubled in every year, this mounting time will soon become the most dominant reason of the delay of system start-up time Therefore, in this paper, we present instant mounting techniques for flash file systems by storing the In-memory file system metadata to flash memory when unmounting the file system and reloading the stored metadata quickly when mounting the file system. These metadata snapshot techniques are specifically developed for NOR- and NAND-type flash memories, while at the same time, overcoming their physical constraints. The proposed techniques check the validity of the stored snapshot and use the proposed fast trash recovery techniques when the snapshot is Invalid. Based on the experimental results, the proposed techniques can reduce the flash mounting time by about two orders of magnitude over the existing de facto standard flash file system, JFFS2.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.13 no.2
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• pp.107-119
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• 1988

An 8-channel digital filter bank with wave digital filters(WDF) is studied. Wave digital filtwr is automatically a directional filter. Using these properties, a new method for organizing the 8-channel digital filter bank is proposed. This will lead to enormous savings in memories for the digital signal processign chip.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1308-1311
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• 2002

We present a low-power MPEG-4 video codec chip capable of delivering high-quality video data in wireless multimedia applications. The discussion will focus on the architectural design techniques for implementing a high-performance video compression/decompression chip at low power architectures. The proposed MPEG-4 video codec can perform 30 frames/s of QCIF or 7.5 frame/s of CIF at 27MHz for 128k∼144kbps. By introducing the efficiently optimized Frame Memory Interface architecture, low power motion estimation and embedded ARM microprocessor and AMBA interface, the proposed MPEG-4 video codec has low power consumption for wireless multimedia applications such as IMT-2000.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.3
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• pp.7-17
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• 2010

In this paper, an innovative low-power SRAM based on 4-transistor latch cell is described. The memory cells are composed of two cross-coupled inverters without access transistors. The sources of PMOS transistors are connected to bitlines while the sources of NMOS transistors are connected to wordlines. They are accessed by totally new read and write method which results in low operating power dissipation in the nature. Moreover, the design reduces the leakage current in the memory cells. The proposed SRAM has been demonstrated through 16-kbit test chip fabricated in a 0.18-${\mu}m$ CMOS process. It shows 17.5 ns access at 1.8-V supply while consuming dynamic power of $87.6\;{\mu}W/MHz$ (for read cycle) and $70.2\;{\mu}W/MHz$ (for write cycle). Compared with those of the conventional 6-transistor SRAM, it exhibits the power reduction of 30 % (read) and 42 % (write) respectively. Silicon measurement also confirms that the proposed SRAM achieves nearly 64 % reduction in the total standby power dissipation. This novel SRAM might be effective in realizing low-power embedded memory in future mobile applications.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.1
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• pp.148-155
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• 2006

Portable embedded systems which mainly handle multimedia applications involve the problem that frequent accesses to fetch data from memory make running time increased. To cope with the problem, embedded processors have adopted data prefetching schemes. From a power point of view, which is a main performance indicator of embedded systems, this paper analyzed to investigate how data prefetching schemes influence on system's performance. To solve the problem, we proposed a power-consumption analysis model of a memory system with data prefetching scheme and measured the power dissipated during running application programs. As a result data prefetching schemes have application program's running time reduced but have system's power increased. Also we proposed a performance analysis model considering execution time and power consumption for embedded system with data prefetching schemes.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.33 no.3
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• pp.427-435
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• 2023

Cardinality estimation is used in wide range of applications and a fundamental problem processing a large range of data. While the internet moves into the era of big data, the function addressing cardinality estimation use only on-chip cache memory. To use memory efficiently, there have been various methods proposed. However, because of the noises between estimator, which is data structure per flow, loss of accuracy occurs in these algorithms. In this paper, we focus on minimizing noises. We propose multiple data structure that each estimator has the number of estimated value as many as the number of structures and choose the minimum value, which is one with minimum noises, We discover that the proposed algorithm achieves better performance than the best existing work using the same tight memory, such as 1 bit per flow, through experiment.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.2
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• pp.29-35
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• 1998

This paper describes architectures and design of a SIMD type parallel image processing chip called SliM-II. The chiphas a linear array of 64 processing elements (PEs), operates at 30 MHz in the worst case simulation and gives at least 1.92 GIPS. In contrast to existing array processors, such as IMAP, MGAP-2, VIP, etc., each PE has a multiplier that is quite effective for convolution, template matching, etc. The instruction set can execute an ALU operation, data I/O, and inter-PE communication simulataneously in a single instruction cycle. In addition, during the ALU/multiplier operation, SliM-II provides parallel move between the register file and on-chip memory as in DSP chips, SliM-II can greatly reduce the inter-PE communication overhead, due to the idea a sliding, which is a technique of overlapping inter-PE communication with computation. Moreover, the bandwidth of data I/O and inter-PE communication increases due to bit-parallel data paths. We used the COMPASS$^{TM}$ 3.3 V 0.6.$\mu$m standrd cell library (v8r4.10). The total number of transistors is about 1.5 muillions, the core size is 13.2 * 13.0 mm$^{2}$ and the package type is 208 pin PQ2 (Power Quad 2). The performance evaluation shows that, compared to a existing array processors, a proposed architeture gives a significant improvement for algorithms requiring multiplications.s.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.2
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• pp.330-338
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• 2002

A speech recognition chip that can recognize a small vocabulary as a word-level has been designed. It is composed of EPD(Start and End-point detection) block, LPC block, DTW block and external memory interface block. It is made of 126,938 gates on 4x4mm2 area with a CMOS 0.35um TLM process. The speed of the chip varies from 5MHz to 60MHz because of its specific hardware designed for the purpose. It can compare 100,000 voices as a small vocabulary which has approximately 50∼60 frames at the clock of 5MHz and also up to 1,200,000 voices at the clock of 60MHz.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.165-168
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• 2002

As the demand for higher data-rate chip-to-chip communication such as memory-to-controller, processor-to-processor increases, low cost high-speed serial links\ulcorner become more attractive. This paper describes a 0.25-fm CMOS 1.6Gbps/pin 4-level transceiver using Stub Series Terminated Logic for high Bandwidth. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by channel low pass effects, process-limited on-chip clock frequency, and serial link distance. The proposed transceiver uses multi-level signaling (4-level Pulse Amplitude Modulation) using push-pull type, double data rate and flash sampling. To reduce Process-Voltage-Temperature Variation and ISI including data dependency skew, the proposed high-speed calibration circuits with voltage swing controller, data linearity controller and slew rate controller maintains desirable output waveform and makes less sensitive output. In order to detect successfully the transmitted 1.6Gbps/pin 4-level data, the receiver is designed as simultaneous type with a kick - back noise-isolated reference voltage line structure and a 3-stage Gate-Isolated sense amplifier. The transceiver, which was fabricated using a 0.25 fm CMOS process, performs data rate of 1.6 ~ 2.0 Gbps/pin with a 400MHB internal clock, Stub Series Terminated Logic ever in 2.25 ~ 2.75V supply voltage. and occupied 500 * 6001m of area.

• Transactions on Electrical and Electronic Materials
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• v.14 no.2
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• pp.63-66
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• 2013

This paper describes the highly productive process technologies of microprobe arrays, which were used for a probe card to test a Dynamic Random Access Memory (DRAM) chip with fine pitch pads. Cantilever-type microprobe arrays were fabricated using conventional micro-electro-mechanical system (MEMS) process technologies. Bonding material, gold-tin (Au-Sn) paste, was used to bond the Ni-Co alloy microprobes to the ceramic space transformer. The electrical and mechanical characteristics of a probe card with fabricated microprobes were measured by a conventional probe card tester. A probe card assembled with the fabricated microprobes showed good x-y alignment and planarity errors within ${\pm}5{\mu}m$ and ${\pm}10{\mu}m$, respectively. In addition, the average leakage current and contact resistance were approximately 1.04 nA and 0.054 ohm, respectively. The proposed highly productive microprobes can be applied to a MEMS probe card, to test a DRAM chip with fine pitch pads.