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The Design of Speech Recognition Chip for a Small Vocabulary as a Word-level  

안점영 (동의대학교 전자공학과)
최영식 (동의대학교 전자공학과)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.6, no.2, 2002 , pp. 330-338 More about this Journal
Abstract
A speech recognition chip that can recognize a small vocabulary as a word-level has been designed. It is composed of EPD(Start and End-point detection) block, LPC block, DTW block and external memory interface block. It is made of 126,938 gates on 4x4mm2 area with a CMOS 0.35um TLM process. The speed of the chip varies from 5MHz to 60MHz because of its specific hardware designed for the purpose. It can compare 100,000 voices as a small vocabulary which has approximately 50∼60 frames at the clock of 5MHz and also up to 1,200,000 voices at the clock of 60MHz.
Keywords
DTW;
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