• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2007.04a
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• pp.477-480
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• 2007

저전력 OFDM(orthogonal frequency division multiplexing) 시스템용 FFT(Fast-Fourier-Transform) LSI를 저전력 동작을 시키기 위해서 FFT LSI는 current-mode 회로로 구현되었다. Current-mode FFT LSI에서, VIC(Voltage-to-current converter)는 입력 전압 신호를 전류로 바꾸는 first main device이다. 저전력 OFDM을 위해 FFT LSI와 VIC가 한 개의 칩과 결합되는 것을 고려하면, VIC는 전력 손실은 낮고, VIC와 FFT LSI 사이에서의 DC offset 전류는 최소인 작은 크기의 chip으로 설계되어야 한다. 본 논문에서는 새로운 VIC를 제안한다. 선형 동작구간을 넓히고 DC offset 전류를 대폭 감소하는 방법을 제시하였다. VIC는 0.35[um] CMOS process로 구현되었으며, 시뮬레이션 결과에 따르면 제안된 VIC는 current-mode FFT LSI와 0.1[uA] 미만의 매우 작은 DC offset 전류, 1.4[V]의 넓은 선형구간을 갖으며, 저전력으로 동작한다.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.1
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• pp.138-145
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• 1995

The offset voltage in silicon Hall plates is mainly caused by stress and strain in package, and by alignment in process. The offset voltage is appeared random for condition change with time in the factory, is non-linearly changed with temperature. In this paper proposed new method of design of Hall IC, and methematicaly proved relation layout of chip of 90$^{\circ}$-shift-current Hall plate pair is matched with "Differentail to single ended Conversion amplifier." In the experiment, the offset voltage is reduced about 1/100 time than the original offset voltage.

• Progress in Superconductivity and Cryogenics
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• v.18 no.2
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• pp.18-20
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• 2016

The study of superconducting fault current limiter (SFCL) is continuously being studied as a countermeasure for reducing fault-current in the power system. When the fault occurred in the power system, the fault-current was limited by the generated impedance of SFCLs. The operational characteristics of the flux-offset type SFCL according to turn ratios between the primary and the secondary winding of a reactor were compared in this study. We connected the secondary core to a superconductor and a SCR switch in series in the suggested structure. The fault current in the primary and the secondary winding of the reactor and the voltage of the superconductor on the secondary were measured and compared. The results showed that the fault current in the load line was the lowest and the voltage applied at both ends of the superconductor was also low when the secondary winding of the reactor had lower turn ratio than the primary. It was confirmed based on these results that the turn ratio of the secondary winding of the reactor must be designed to be lower than that of the primary winding to reduce the burden of the superconductor and to lower the fault current. Also, the suggested structure could increase the duration of the limited current by limiting the continuous current after the first half cycle from the fault with the fault current limiter.

• Proceedings of the KIPE Conference
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• 2013.07a
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• pp.130-131
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• 2013

In this paper, it suggests offset compensation method of output current in single phase PV-BES system which is connected with grid. The algorithm applied removes grid's frequency ingredient using a notch filter and it extracts only DC offset current. It can reduce problems as saturation of power transformer cause by DC current when it is indoctrinated to grid.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.6
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• pp.1108-1114
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• 2016

The cause of failure in the AT feeding system is divided into grounding, short-circuit of feeding circuit and internal faults of the railway substation. Since the fault current is very high, real-time current is detected and the failure must be immediately removed. In this paper, a new DC offset elimination filter that can remove component to decrease in the form of exponential function using low-pass filter was proposed in order to extract the fundamental wave from distorted fault current. In order to confirm the performance of the proposed filter method, AT feeder system was modelled by simulation tool and simulations were performed under various conditions such as fault location, fault resistance and fault voltage phase angle in case of trolley-rail short-circuit fault. When applying the proposed DC-offset removal method, it can be seen that the phase delay and gain error did not appear.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.5
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• pp.900-905
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• 2008

I perform bit error rate(BER) analysis of orthogonal frequency division multiplexing(OFDM) systems impaired by both direct current(DC) offset and carrier frequency offset. By analyzing the BER performance for real OFDM systems employing 16-quadrature amplitude modulation(QAM) and pilot symbol estimation, the dependency of BER on the DC offset and carrier frequency offset is quantified and compared to ideal performance. Results show that the magnitude of frequency offset and DC offset are required to be less than 0.01 and 0.007, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.347-353
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• 2017

We present a STT-MRAM read-circuit which mitigates the performance degradation caused by offsets from device mismatches. In the circuit, a single current source supplies read-current to both the data and the reference cells sequentially eliminating potential mismatches. Furthermore, an offset-free pre-amplification using a capacitor storing the mismatch information is employed to lessen the effect of the comparator offset. The proposed circuit was implemented using a 130-nm CMOS technology and Monte Carlo simulations of the circuit demonstrate its effectiveness in suppressing the effect of device mismatch.

• Journal of electromagnetic engineering and science
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• v.8 no.3
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• pp.134-137
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• 2008

This paper proposes a novel quadrature VCO(QVCO) based on direct back-gate second harmonic coupling. The QVCO directly couples the current sources of the conventional LC VCOs through the back-gate instead of front-gate to generate quadrature signals. By the second harmonic injection locking, the two LC VCOs can generate quadrature signals without using on-chip transformer, or stability problem that is inherent in the direct front-gate second harmonic coupling. The proposed QVCO is implemented in $0.18{\mu}m$ CMOS technology operating at 2 GHz with 5.0 mA core current consumption from 1.8 V power supply. The measured phase noise of the proposed QVCO is - 63 dBc/Hz at 10 kHz offset, -95 dBc/Hz at 100 kHz offset, and -116 dBc/Hz at 1 MHz offset from the 2 GHz output frequency, respectively. The calculated figure of merit(FOM) is about -174 dBc/Hz at 1 MHz offset. The measured image band rejection is 46 dB which corresponds to the phase error of $0.6^{\circ}$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.11 no.6
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• pp.388-395
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• 1986

Dispersion characteristics of shielded single, coupled and edge-offset microstrip structures are investigated by using hybrid mode analysis with Galerkin's method in the spectral domain. Two new basis functions for the longitudinal strip current are proposed and convergence rates of the solutions for the basis functions are compared. Current distribution of the coupled line is obtaind from that of the single line by using shift theorem of the Fourier transform. In addition, effects of off-centered inner strip conductor on dispersion are also discussed Numerical results include various structual parameters and are compared with other available data and good agreements are observed.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.19 no.8
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• pp.116-121
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• 2005

To realize the tap coefficient of a finite impulse response(FIR) filter or the twiddle factor of a fast Fourier transform(FFT) using a current-mode analog circuit, a high accurate current-attenuator circuit is needed This paper introduces an accuracy enhancement technique in the current-mode signal processing. First of all, the DC of set-current error in a conventional current-attenuator using a gate-ratioed orient mirror circuit is analyzed and then, the current-attenuator circuit with a negligibly small DC offset-current error is introduced. The circuit consists of N-output current mirrors connected in parallel with me another. The output current of the circuit is attenuated to 1/N of the input current. On the basis of the Kirchhoff current law, the current scale ratio is determined simply by the number of the current mirrors in the N-current mirrors connected in parallel. In the proposed current-attenuator circuit the scale accuracy is limited by the ac gain error of the current mirror. Considering that a current mirror has a negligibly small ac gain error, the attainable maximum scale accuracy is theoretically -80[dB] to the input current.