• Proceedings of the KIPE Conference
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• 2010.07a
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• pp.434-435
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• 2010

본 논문에서는 배전급 고전압(1kV~7.2kV) 계통 연계가 가능한 새로운 3 병렬 3 레벨 NPC(Neutral-Point-Clamped) 컨버터/인버터 회로방식을 제안한다. 이 회로방식은 정격 용량의 1/3 크기를 가지는 NPC 컨버터/인버터 모듈을 3 병렬로 구성하면서 직류단 캐패시터를 병렬 연결하여 중성점 전위 변동을 저감할 수 있는 특징을 가진다. 제안된 3 병렬 3 레벨 NPC 컨버터/인버터는 기존의 NPC 컨버터의 장점을 가지면서 동시에 용량 확장이 가능하고, 하나의 모듈이 고장 상태가 되더라도 부분 운전이 가능하여 시스템의 신뢰성을 증대시킬 수 있다. 본 논문에서는 제안된 중성점 전압 제어 전략을 실험을 통하여 검증한다. 정밀한 중성점 전압 제어를 위한 중성점 전류 제어 방법이 3병렬 구조에서 안정적으로 동작함을 컴퓨터 모의 실험을 통해 검증한다.

• Proceedings of the KIPE Conference
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• 2018.07a
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• pp.316-317
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• 2018

This paper propse the DC link capacitor voltage balancing control for three level neutral point clamped converter with harmonic component injection method. The injcetion voltage consists of harmonic component and DC link capacitor voltage difference. Theoretical analysis is provided to balance the DC link voltage, and it shows that harmonic component compensates the unbalanced condition between the capacitors. Both simulations and experiments are carried out to show that the voltage unbalance have been decreased by the proposed method.

• Journal of Power Electronics
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• v.16 no.6
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• pp.2076-2084
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• 2016

In this paper, a novel scheme to eliminate common-mode voltage (CMV) is proposed for three-level neutral-point clamped (NPC) inverters. In the proposed scheme, a low-power full-bridge converter is utilized to produce compensatory voltage for CMV, which is injected into an NPC inverter through a single-phase four-winding transformer. With the proposed circuit, the power range for applications is not limited, and the maximum modulation index of the inverter is not reduced. These features are suitable for high-power medium-voltage machine drives. The effectiveness of the proposed method is verified by simulation and experimental results.

• Journal of Electrical Engineering and Technology
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• v.13 no.1
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• pp.362-371
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• 2018

This work proposes FPGA implementation of Carrier Disposition PWM for closed loop seven level diode clamped multilevel inverter in speed control of induction motor. VLSI architecture for carrier Disposition have been introduced through which PWM signals are fed to the neutral point seven level diode clamped multilevel using which the speed of the induction motor is controlled. This proposed VLSI architecture makes the power circuit to work better with reduced stresses across the switches and a very low voltage and current total harmonic distortion (THD). The output voltages, currents, torque & speed characteristics for seven level neutral point diode clamped multilevel inverter for AC drive was studied. It has observed the proposed scheme introduces less distortion and harmonics. The results were validated using real time results.

• Journal of Power Electronics
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• v.11 no.5
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• pp.688-696
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• 2011

This paper proposes a simple space vector PWM (SVPWM) scheme including overmodulation operation for 3-level NPC (Neutral Point Clamped) Inverters. The proposed scheme features a simple decision and calculation procedure for determining switching times in the overmodulation range by utilizing the duty calculation method used in 2-level inverters and the minimum phase error projection method widely employed in motor drive systems. The proposed scheme does not need to detect the angle of the reference vector or calculate trigonometric functions to determine the magnitude of the voltage vector. The magnitude of the angle of the new reference voltage vector is decided in advance with the help of the Fourier Series Expansion to extend the linearity of the output voltage of 3-level inverters in the overmodulation region. Experimental results demonstrate the validity of the proposed SVPWM scheme including overmodulation operation for 3-level NPC inverters.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.3
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• pp.257-265
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• 2014

This paper proposes a simple compensation method for switches of the unclamped voltage in the three-level NPC inverter. Voltages of inner-switches can be unclamped in the three-level NPC (neutral point clamped) inverter. It can cause the problem of the switch fault accident. By adding a capacitor, switches of the unclamped voltage can be clamped. Through the analysis of the circuit, the reason behind switches being unclamped was verified which leads to the solution method that designs a compensation capacitor. The proposed method was validated through the simulation and experimental results.

• The Transactions of the Korean Institute of Power Electronics
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• v.22 no.6
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• pp.535-542
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• 2017

This paper proposes a simple 3-level interleaved charger-discharger for the uninterruptible power supply (UPS) with various combinations of battery cells. The proposed converter not only improves charging and discharging efficiency, but also reduces the physical volume and the cost. Furthermore, the converter also offers the capability of the neutral point voltage, so that more stable operation can be obtained. In addition, the proposed converter significantly reduces the ripple current of the battery inductor, thereby providing an expected life extension of the battery. Experimental results for a 300kVA UPS prototype verify the validity of the proposed converter. The proposed charger-discharger is suitable for UPSs and energy storage systems (ESSs) with wide input battery voltage ranges.

• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.315-316
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• 2015

본 논문에서는 3-레벨 Neutral-Point-Clamped (NPC) 인버터의 DC-Link 중성점 전압 리플을 저감하여 인버터 출력 전압의 품질 신뢰성 향상이 가능한 새로운 Discontinuous Pulse Width Modulation (DPWM) 기법을 제안한다. NPC 인버터에서는 두 개의 커패시터로 이루어진 DC-Link 구조로 인해 상, 하단 DC-Link 커패시터 전압 불평형인 상황에서 DC-Link 중 성점 전압 리플이 발생한다. 중성점 전압 리플 발생 시 출력 전압의 품질을 보장할 수 없으며, 민감한 부하에 손상을 입힐 수 있다. 제안한 DPWM 알고리즘은 DC-Link 커패시터 전압을 조정하는 두 개의 오프셋을 사용하여 중성점 전압 리플을 저감한다. 또한, 시뮬레이션을 통해 본 논문에서 제안한 알고리즘의 타당성을 검증한다.

• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.315-316
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• 2012

Three-level neutral point clamping (NPC) converter has been widely applied in high power drive system. And in this paper, a novel method is proposed to realize this algorithm based on FPGA, And the system is consist of two parts, the DSP part and FPGA part, the DSP part includes the control algorithms and the FPGA part works to generate and putout 12 PWM pulses. And the system is tested and verified using both simulation and experimentation.

• Communications for Statistical Applications and Methods
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• v.27 no.2
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• pp.211-224
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• 2020

Sensitivity and specificity are popular measures described by the receiver operating characteristic (ROC) curve. There are also two other measures such as the positive predictive value (PPV) and negative predictive value (NPV); however, the PPV and NPV cannot be represented by the ROC curve. Based on the total operating characteristic (TOC) curve suggested by Pontius and Si (International Journal of Geographical Information Science, 97, 570-583, 2014), explanatory methods are proposed to geometrically describe the PPV and NPV by the TOC curve. It is found that the PPV can be regarded as the slope of the right-angled triangle connecting the origin to a certain point on the TOC curve, while 1 - NPV can be represented as the slope of the right-angled triangle connecting a certain point to the top right corner of the TOC curve. When the neutral zone exists, the PPV and 1-NPV can be described as the slopes of two other right-angled triangles of the TOC curve. Therefore, both the PPV and NPV can be estimated using the TOC curve, whether or not the neutral zone is present.